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Semiconductor device and manufacturing method thereof

A semiconductor and device technology, applied in the field of semiconductor devices and their manufacturing, can solve problems such as high resistance of impurity diffusion layers or increased joint leakage, and achieve the effect of inhibiting abnormal growth and condensation

Inactive Publication Date: 2006-11-08
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, problems arise such that the impurity diffusion layer has a high resistance or the bonding leakage increases.

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

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Effect test

no. 1 example

[0043] figure 1 is a cross-sectional view showing the configuration of the semiconductor device of the present embodiment. In the present embodiment, the semiconductor device 100 is a CMOS (Complementary Metal Oxide Semiconductor) device including an N-type MOSFET 118 and a P-type MOSFET 120 . In addition, this CMOS device constitutes the internal circuit of the LSI.

[0044] The semiconductor device 100 includes: a silicon substrate 102, a P-well 102a of a P-type conductor and an N-well 102b of an N-type conductor; and an element isolation region 104 for isolating the P-well 102a and the N-well 102b. N-type MOSFET 118 and P-type MOSFET 120 are formed at P-well 102a and N-well 102b, respectively. Interlayer insulating film 134 covering the sides of N-type MOSFET 118 and P-type MOSFET 120 is formed on silicon substrate 102 .

[0045] A pair of impurity diffusion layers 121 are provided at the P well 102a, and a channel region is formed between these impurity diffusion layers...

no. 2 example

[0082] In the present embodiment, a part of the process for manufacturing the semiconductor device 100 is different from the first embodiment. The following is a reference Figure 5A to 5C are descriptions of the method of manufacturing the semiconductor device of the present embodiment. Figure 5A to 5C are process sectional views showing a part of the process of manufacturing the semiconductor device 100 of the present embodiment.

[0083] Likewise, in this embodiment, use the same reference as in the first embodiment Figures 2A to 2C , 3A and 3B described the same process formed with Figure 3B The structure shown is the same structure. The protective film 140 is selectively removed by, for example, dry etching, and the polysilicon film 114 is exposed ( Figure 5A ).

[0084] Next, a second metal layer 144 (having a film thickness of, for example, 5 nm to 10 nm) is formed on the entire surface on the silicon substrate 102 ( Figure 5B ). Thereafter, a second heat tr...

no. 3 example

[0088] In the present embodiment, a part of the process for manufacturing the semiconductor device 100 is different from the first embodiment. The following is a reference Figures 6A to 6C , 7A, 7B, and 8A to 8C are descriptions of the method of manufacturing a semiconductor device of the present embodiment. Figures 6A to 6C , 7A, 7B, and 8A to 8C are process cross-sectional views showing a part of the process of manufacturing the semiconductor device 100 of the present embodiment.

[0089] First, as described in the first embodiment, the element isolation region 104, the P well 102a, and the N well 102b are formed on the silicon substrate 102, and the gate insulating film 106 and the polysilicon film 114 are formed on the silicon substrate 102 ( Figure 6A ). This embodiment differs from the first embodiment in that protective film 140 is not formed on polysilicon film 114 .

[0090] Next, selective etching is performed to form a gate shape in such a manner that a predet...

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Abstract

A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate and containing a gate electrode; impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of the gate electrode, of a region on which the semiconductor element is formed of the semiconductor substrate; first silicide films formed respectively at the surface of the impurity diffusion layers, composed of a silicide compound of a first metal; and a second silicide film, formed at least at the surface of the gate electrode, composed of a silicide compound of a second metal different to the first metal. The silicide compound of the second metal has a silicidation temperature lower than the silicidation temperature of the silicide compound of the first metal.

Description

[0001] This application is based on Japanese Patent Application No. 2005-135188, the contents of which are incorporated herein by reference. technical field [0002] The present invention relates to a semiconductor device in which a silicide film is formed at a gate electrode and an impurity diffusion layer and a method of manufacturing the same. Background technique [0003] A technique for siliciding the surface of a gate electrode of a transistor made of polysilicon or the surface of an impurity diffusion layer constituting a source region or a drain region of a transistor to realize low resistance of these regions is well known. It is possible to make the transistor operate at high speed by making the constituent parts of the transistor low in resistance. [0004] Conventionally, after forming a gate insulating film, a gate electrode, a side wall insulating film, and an impurity diffusion layer of a transistor, by forming a metal layer on the polysilicon of the gate elec...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/772H01L21/335H01L21/336H01L21/8238H01L27/092H01L29/78
CPCH01L21/28097H01L21/28518H01L29/66507H01L29/66545H01L29/78H01L2924/0002H01L2924/00
Inventor 君冢直彦今井清隆
Owner NEC ELECTRONICS CORP
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