Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Dry etch post process method

A technology of dry etching and processing chambers, which is applied in the field of semiconductor manufacturing technology, can solve the problems of product electrical connection errors, low yield, and difficulty in completely removing polymers, etc., to achieve the effect of improving product yield and avoiding electrical connection errors

Inactive Publication Date: 2006-01-18
HONG FU JIN PRECISION IND (SHENZHEN) CO LTD +1
View PDF2 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In order to overcome the defect that the dry etching post-processing method in the prior art is difficult to completely remove the polymer, which leads to product electrical connection errors and low yield, the present invention provides a dry etching post-processing method with higher yield

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Dry etch post process method
  • Dry etch post process method
  • Dry etch post process method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] see Figure 4 to Figure 8 , is a schematic diagram of dry etching to form the source and drain layers (Sourceelectrode&Drain electrode, SD) of the thin film transistor. see Figure 4 , is a deposition step, depositing the SD metal layer 50 on the glass substrate 10 , and then depositing a passivation layer 40 on the SD metal layer 50 and the substrate 10 . see Figure 5 , is a photomask process, coating photoresist on the passivation layer 40, and then exposing the photoresist through a photomask to form the photoresist layer 30 with openings. see Figure 6 , is a dry etching step, using O in a dry etching chamber (not shown) 2 , SF 6 and CF 4 The gas etches a portion of the passivation layer 40 to form a contact hole 70, during which a polymer layer 60 is formed and covers the contact hole 70 and the like. see Figure 7 , is a post-dry etch processing step using SF 6 Ashing is performed to remove the polymer layer 60 . see Figure 8 , is a photoresist stripp...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This invention relates to a method for dry etching treatment, characterized in using SF6 gas into room, and ashing the surface of product after dry etching treatment and residue on the dry etched wall in room. The method can effectively eliminate the dry-etching residue and guarantee the product quality, clean the device, reduce the times of cleaning and servicing device and lengthen the time of usage.

Description

【Technical field】 [0001] The invention relates to a semiconductor manufacturing process, in particular to a post-dry etching treatment method. 【Background technique】 [0002] Dry etching (Dry Etching) is a processing method widely used in the semiconductor industry. It usually first covers the photoresist layer on the semiconductor layer to be etched, and then uses a photomask to expose the photoresist layer to form a specific pattern, and then introduces a dry etching gas such as O into the etching chamber. 2 , SF 6 and CF 4 Etching the semiconductor layer, and finally forming a predetermined pattern on the semiconductor layer to be etched under the protection of the photoresist layer. [0003] However, during the dry etching reaction, a polymer is generated and deposited on the semiconductor layer. Due to the high resistance of the polymer, it is easy to cause an electrical connection error of the product. It is therefore necessary to employ a post-treatment step for t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/3065H01L21/311H01L21/00
CPCH01L21/02063
Inventor 邱立峰高胜洲黄荣龙欧振宪黄昌桂陈青枫
Owner HONG FU JIN PRECISION IND (SHENZHEN) CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products