12T radiation-proof SRAM (Static Random Access Memory) storage unit based on polarity strengthening technology

Abstract

The invention discloses a 12T radiation-proof SRAM (Static Random Access Memory) storage unit based on a polarity strengthening technology. The 12T radiation-proof SRAM storage unit comprises four NMOS (N-channel Metal Oxide Semiconductor) transistors and eight PMOS (P-channel Metal Oxide The internal storage nodes I2 and I3 are cross-coupled by P2 and P3, and the external storage nodes I1 and I4 are cross-coupled by N1 and N2; the P1 and the P4 are used as pull-up tubes, the P1 and the P4 are used for reinforcing the I2 and the I3, and the I2 and the I3 are both surrounded by the PMOS transistors, so that a polarity reinforcing structure is formed; i2 is connected to the BLB through P7, I3 is connected to the BL through P8, I1 is connected to the BL through N3, I4 is connected to the BLB through N4, N3 and N4 are controlled by WL, and P7 and P8 are controlled by WWL. According to the invention, the single event upset resistance of the SRAM storage unit can be improved, the writing speed of the SRAM storage unit can be greatly improved under the condition of sacrificing a small unit area, and the power consumption of the SRAM storage unit is reduced.

Description

technical field [0001] The invention relates to the technical field of SRAM (Static Random Access Memory, static random access memory in Chinese), in particular to a 12T (12T refers to 12 CMOS tubes) radiation-resistant SRAM storage unit based on polarity reinforcement technology, which is a The unit circuit structure that can improve the writing speed of the storage unit and the anti-single event upset (Single Event Upset, SEU) capability of the unit is hereinafter referred to as RHMC-12T. Background technique [0002] With the rapid development of the integrated circuit industry, SRAM has become a key component of high-performance integrated circuits (ICs). In aerospace electronic equipment, integrated circuit chips are almost indispensable components, and aerospace electronic equipment is often in the space radiation environment. Once high-energy particles from cosmic rays hit a sensitive node of the storage unit, it will occasionally cause a temporary single event Flip ...

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Problems solved by technology

[0004] (1) if figure 1 The circuit shown is a Soft Error Tolerant 10T SRAM BitCell (QUATRO 10T) circuit proposed by Shah M.Jahinuzzamandeng and David J.Rennie in 2009. It consists of four PMOS transistors and six NMOS transistors, of which there are two NOMS transistors are used as pass transistors; this circuit has poor write capability, high write delay, and high write failure rate at high frequencies

[0005] (2) if figure 2 The circuit shown is a basic 6T SRAM memory cell consisting of two PMOS transistors and four NMOS transistors; this memory cell uses the fewest number of transistors and therefore has the smallest area, but the circuit does not have any Ability to flip nodes

[0006] (3) if image 3 The circuit shown is a soft-error-aware-14T (SEA14T) circuit proposed by Soumitra Pal in 2021, which is composed of six PMOS transistors and eight NMOS transistors, of which two NMOS transistors are used as pass transistors; it Although it has good anti-SEU ability, the area consumed by the circuit is large and the write data delay is high

[0007] (4) if Figure 4 The circuit shown is the Quadruple Cross-CoupledMemory (QCCM12T) circuit proposed by Aibin Yan in 2019. It uses four access transistors, has low read and write access times, and can better tolerate single-node flipping and a few dual The node pair is flipped, but the circuit has a large static power consumption

[0008] (5) if Figure 5 The circuit shown is a soft-errorresilient read decoupled 12T (SRRD12T) circuit proposed by Soumitra Pal in 2021, which is composed of eight PMOS transistors and four NMOS transistors, of which two NMOS transistors and two PMOS transistors As a pass transistor, it has low write latency but high read latency

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