On-chip core compiling and mapping method and device of neural network based on reinforcement learning

Abstract

The invention discloses an on-chip core compilation mapping method and device for a neural network based on reinforcement learning, and the method comprises the steps: putting a conventional mapping planning problem into a reinforcement learning framework, constructing a state description, a reward function and an action space, and obtaining a strategy deep network through reinforcement learning training. Neurons are sequentially placed within a plurality of cores of a network-on-chip. The mapping income is constructed by communication cost, mapping area and core internal utilization rate, the strategy network is trained by using an Actor-Critic algorithm to obtain higher mapping income, and the reinforcement learning strategy network is trained to learn the optimal mapping position of any pulse neural network neurons. And finally, finishing from the neural network needing to be deployed to the on-chip core array by using the trained strategy network, thereby reducing the on-chip communication distance cost of the interconnected neurons, effectively improving the chip calculation efficiency and reducing the overall power consumption.

Description

technical field [0001] The invention relates to the field of computer high-performance computing, in particular to an on-chip core compiling and mapping method and device based on a reinforcement learning neural network. Background technique [0002] Neuroscience research on the human brain has found that tens of billions of neurons can generate a high degree of parallel computing power through interconnection, and the pulse neural network proposed on this basis can complete information transmission through pulse coding to solve complex tasks. The neuromorphic chip based on the spiking neural network simulates the connection of biological neurons with a high-density on-chip network organization, and realizes the parallelization of large-scale computing. However, the information communication mode between different cores of the network on chip is very sensitive to the generation and transmission of pulses, which puts forward extremely high requirements on the performance cons...

AI Technical Summary

Problems solved by technology

Too simple a mapping scheme cannot quickly search for the optimal solution in a huge solution space, and it is easy to fall into the local suboptimal solution caused by the unreasonable design of the mapping algorithm and cost function, resulting in slow transmission of pulse packets between cores , resulting in additional communication and power consumption

Images