Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a substrate; forming a hard mask material layer on the substrate; forming a discrete barrier layer on the hard mask material layer, wherein the material of the barrier layer is a metal-containing polymer; using the barrier layer as a mask, performing ion doping treatment on the hard mask material layer, so that the etching resistance of the hard mask material layer is increased, the hard mask material layer doped with ions is used as a hard mask layer, and the hard mask material layer not doped with ions is used as a sacrificial layer; removing the barrier layer; forming a first groove penetrating through the hard mask layer between the adjacent sacrificial layers, wherein the first groove is isolated from the sacrificial layers; after the first groove is formed, removing the sacrificial layer to form a second groove; and etching the substrate at the bottoms of the first groove and the second groove by taking the hard mask layer as a mask to form a target pattern. The embodiment of the invention is favorable for improving the pattern transfer precision.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the rapid growth of the semiconductor integrated circuit (Integrated circuit, IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits smaller in size, higher in circuit precision, and development in the direction of higher complexity. [0003] During the development of integrated circuits, usually as the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) also gradually decreases. Correspondingly increases the difficulty and complexity of integrated circuit manufacturing. [0004] At present, how to improve the matching deg...

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Problems solved by technology

[0003] During the development of integrated circuits, usually as the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) also gradually decreases. Correspondingly increases the difficulty and complexity of integrated circuit manufacturing

[0004] At present, in the case of shrinking technology nodes, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge

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