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Pipeline scheduling method and device

A scheduling device and scheduling method technology, which is applied to multi-programming devices, machine execution devices, instruments, etc., can solve the problems of irrelevant service types, difficult to meet the ultra-low latency of 5G networks at the same time, and complex packet service processing pipelines, etc. The effect of flexible connection, strong scalability, and optimized transmission delay

Active Publication Date: 2020-11-03
FENGHUO COMM SCI & TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] NP (network processor, network processor) pipeline technology is the core technology of network processors. The traditional NP pipeline is often determined by the physical pipeline length of the chip, and the length is generally fixed. It has nothing to do with the type of business and cannot be flexibly adapted. Business processing requirements, the forwarding delay of various services is basically the same, and the optimization of processing mainly depends on microcode application developers
In order to cope with the application requirements of massive connections and enhanced bandwidth in 5G networks, the traditional packet service processing pipeline is becoming more and more complex, and the main frequency design requirements are getting closer and closer to the limit of Moore's law realized by semiconductor physics. It is difficult for its architecture to meet the ultra-low latency in 5G networks at the same time requirements

Method used

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Embodiment 1

[0042] An embodiment of the present invention provides a pipeline scheduling device, including three physical pipelines, two mixbuffers and a bus pipe bus, wherein:

[0043] The three physical pipelines are logically divided into five pipelines, corresponding to the five stages of message processing in the chip: parse, bridge, router, post and egress;

[0044] The two mix buffers are used to schedule different services, and then send them into the corresponding logic pipeline;

[0045] Each pipeline unit pipe, mix buffer and pdsrc are connected to the bus pipe bus to complete the interaction between each pipeline unit.

[0046] Specifically, the new pipeline scheduling device changes the traditional two physical pipelines into three physical pipelines, and logically divides them into five pipelines, corresponding to the five stages of message processing in the chip: parse, bridge, router, post, egress.

[0047] Since the message jumps between the pipelines, the present inven...

Embodiment 2

[0050] Such as figure 1 As shown, various pipeline units are mounted on the bus pipe bus provided by the embodiment of the present invention, including pdsrc, two mix buffers and pipe, wherein:

[0051] Pdsrc mainly completes the packet descriptor generation of the message entering the pipeline, and the message descriptor enters the pipe for processing;

[0052] Mix buffer completes the processing instruction jump switching and scheduling of message descriptors between pipes;

[0053] Pipe completes specific message processing, and the specific processing process is filled by developers using microcode.

[0054] Further, in the embodiment of the present invention, the two mix buffers include a first mix buffer and a second mix buffer, wherein the first mix buffer includes high, medium, and low priority queues, and the second mix buffer includes high , medium, and low priority queues.

Embodiment 3

[0056] The embodiment of the present invention provides a logical division method of a physical pipeline, which logically divides three physical pipelines into five pipelines, specifically:

[0057] The first physical pipeline pipe0 is divided into two logical processing pipelines: parse and post;

[0058] The second physical pipeline pipe1 is divided into two logical processing pipelines, bridge and router;

[0059] The third physical pipeline Pipe2 corresponds to the egress logic pipeline.

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Abstract

The invention discloses an assembly line scheduling device, which comprises three physical assembly lines, two mix buffers and a bus pipe bus, and is characterized in that the three physical assemblylines are logically divided into five assembly lines, and the five assembly lines respectively correspond to five stages of processing messages in a chip, i.e., a parse stage, a bridge stage, a routerstage, a post stage and an egress stage; the two mix buffers are used for scheduling different services and then sending the different services to the corresponding logic assembly lines; and each pipeline unit pipe, the mix buffer and the pdsrc are hung on the bus pipe bus and are used for completing the interaction among the pipeline units. According to the invention, various services are optimized in the aspect of assembly line processing length, and different services can correspond to different processing lengths, so that unnecessary processing is reduced; the pipe bus is used for replacing the original connection relationship among the members of the assembly line, so that the members of the assembly line are connected more flexibly, the expandability is very high, and the new requirements in the future can be met. The invention further provides a corresponding assembly line scheduling method.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chips, and more specifically relates to a pipeline scheduling method and device. Background technique [0002] NP (network processor, network processor) pipeline technology is the core technology of network processors. The traditional NP pipeline is often determined by the physical pipeline length of the chip, and the length is generally fixed. It has nothing to do with the type of business and cannot be flexibly adapted. For business processing requirements, the forwarding delays of various services are basically the same, and the optimization of processing mainly depends on microcode application developers. In order to cope with the application requirements of massive connections and enhanced bandwidth in 5G networks, the traditional packet service processing pipeline is becoming more and more complex, and the main frequency design requirements are getting closer and closer to the limit of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/865H04L12/863G06F9/54G06F9/48G06F9/38H04L47/6275
CPCH04L47/6275H04L47/6295G06F9/3836G06F9/4881G06F9/546G06F2209/5021G06F2209/548
Inventor 陈永洲邓作
Owner FENGHUO COMM SCI & TECH CO LTD
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