Trench silicon carbide power device with low on-resistance and manufacturing process thereof

Abstract

The invention provides a trench silicon carbide power device with low on-resistance and a manufacturing process thereof. The cell of the trench silicon carbide power device comprises an N-type substrate, an N-type epitaxial layer and a trench, wherein the trench is internally provided with a gate oxide layer and a polysilicon gate, a P-type body region, an N-type source region and a P+ body contact region are arranged on the two sides of the trench, a P shielding layer is arranged below the trench, and an N-type buried layer is arranged on the side of the P shielding layer. The manufacturing process of the N-type buried layer comprises the steps of epitaxially growing a first part of an N-type drift region on the N-type substrate, forming a P shielding layer and an N-type buried layer on the first part of the N-type drift region by adopting an ion implantation process, continuing to epitaxially form a second part of the N-type drift region, and carrying out a subsequent process flow. According to the invention, two sides of the P shielding layer are provided with the N-type buried layers, the electric field peak is moved downwards, the trench corner electric field is reduced, the interface state density and defects are reduced, and the reliability of the gate oxide layer is improved; and an N-type buried layer below is eliminated, the gate charge of the device is reduced, the switching characteristic is improved, and the withstand voltage of the device is further improved.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a silicon carbide trench MOS device and a manufacturing process thereof. Background technique [0002] The third-generation wide-bandgap semiconductor material SiC has the advantages of high saturation drift speed and high thermal conductivity. It is widely used in the field of power semiconductors and has good development prospects. Compared with Si-type MOSFETs, MOSFETs made of SiC materials effectively reduce the device volume. , improved integration. Compared with the planar gate MOS device, the trench type MOS device eliminates the JFET region, increases the channel density and reduces the on-resistance of the device. However, today's trench-type silicon carbide devices still have shortcomings, such as the corners of trench-type devices are prone to breakdown, so a P-type shielding layer is usually introduced under the trench to optimize the electri...

AI Technical Summary

Problems solved by technology

However, today's trench-type silicon carbide devices still have shortcomings, such as the corners of trench-type devices are prone to breakdown, so a P-type shielding layer is usually introduced under the trench to optimize the electric field distribution at the corners, which can effectively improve the reliability of the device. But this also introduces additional JFET area, which increases the on-resistance of the device

To this end, the researchers proposed an N-type buried layer all-encapsulated P shielding layer structure, which effectively reduces the width of the JFET region and reduces the on-resistance; however, this structure introduces the peak value of the electric field into the sharp corner of the trench. , will cause the oxide layer to degrade or break down, cause device failure or increase gate leakage, and reduce device reliability; and this structure introduces a high-concentration PN junction at the main junction, which reduces the device withstand voltage; at the same time, the N under the P-type shielding layer The excess electrons are introduced into the open-state region, which increases the gate charge of the device and deteriorates the switching characteristics.

In addition, the one-stage process flow of the existing trench-type devices is complicated, the process is difficult, the trench etching accuracy is poor, and a large number of defects are introduced into the channel of the SiC device, resulting in an excessively high interface state density and affecting device performance.

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