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Time domain A/D converter group

A converter and time-domain technology, applied in analog-to-digital converters, analog-to-digital conversion, code conversion, etc., can solve the problem of increased area, increased power consumption, and A/D converters that cannot be high-speed and low-power. Achieving high dynamic range of sensors, etc.

Active Publication Date: 2020-08-14
TECH IDEA CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in order to suppress noise, a large capacitor of 10pF to 20pF is often used, resulting in not only an increase in area, but also an increase in power consumption
[0025] Therefore, A / D converters used in existing sensor devices cannot achieve the high dynamic range required by sensors at high speed and low power consumption

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach

[0138] (A / D converter using two reference voltage signals)

[0139] figure 1 The A / D converter 60 according to the first embodiment of the present disclosure is shown. The A / D converter 60 according to the first embodiment includes a comparator 12, an internal A / D converter 30, a reference voltage selection circuit 63, and an accumulation adder-subtractor 64, wherein the reference voltage selection circuit 63 has two kinds of ramp signals Serving as a reference voltage and switching between the reference voltages, the accumulative adder-subtractor 64 is used to perform accumulative addition or accumulative subtraction on a plurality of converted values ​​and output the averaged output as an A / D converted value.

[0140] In the A / D converter 60 according to the first embodiment, the comparator 12 compares the pixel signal with the ramp signal as the reference voltage signal, generates a comparison output at the time when the two signals intersect, and controls the counter to ...

no. 2 approach

[0194] (A time-domain A / D conversion module including multiple A / D converters using a multi-phase clock formed by a DLL circuit)

[0195] Figure 14 A time-domain A / D conversion module including a plurality of A / D converters according to an embodiment of the present disclosure is shown. The A / D conversion module 10 includes a DLL (delay locked loop) circuit 20, and also includes a plurality of comparators 12-1, 12-2, ..., 12-n (n is a natural number, hereinafter, without distinguishing each comparator 12) and a plurality of internal A / D converters 30-1, 30-2, . A plurality of A / D converters 14-1, 14-2, . / D converter 14).

[0196] The DLL circuit 20 includes a plurality of delay circuits 21-1, 21-2, 21-3, and 21-4 (hereinafter referred to as delay circuits 21 when the respective delay circuits are not distinguished), a phase comparator (PD) 22, a charge pump (CP) and low pass filter (LPF) 23 . Four-stage delay circuits 21 - 1 , 21 - 2 , 21 - 3 , and 21 - 4 arranged in ser...

no. 3 approach

[0207] (conversion from polyphase clock signal to Gray code)

[0208] Figure 17 An A / D conversion module according to a third embodiment of the present disclosure is shown. The A / D conversion module 90 according to the third embodiment differs from the A / D conversion module 10 according to the second embodiment in that it further includes a Gray circuit between the DLL circuit 20 and the internal A / D converter 30 Code converter 50. The same description as the second embodiment is omitted, and the parts different from the A / D conversion module 10 according to the second embodiment are described here.

[0209] The Gray code converter 50 converts the multiphase clock signal 15 output from the DLL circuit 20 from a thermometer code (thermometric code) into a Gray code, and then inputs it to a latch or a trigger of a TDC unit constituting each internal A / D converter 30. Device 31. By configuring in this way, the number of latches constituting the TDC can be greatly reduced, an...

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Abstract

The invention provides a time domain A / D converter group that comprises a plurality of A / D converters. Each A / D converter comprises: a delay lock loop circuit, which takes a main clock supplying a clock to an integrated circuit as an input, performs frequency division on the main clock to output a multi-phase clock with different time sequences; a logic circuit, which synthesizes a plurality of clocks corresponding to Gray codes according to the multi-phase clock; and a plurality of A / D converters next to each other in space. The delay lock loop circuit and the logic circuit are dispersed in the integrated circuit; the A / D converters supply multiple clocks to one A / D converter module; each A / D converter comprises a comparator that compares an input signal with a reference voltage to generate a comparison output signal and an internal A / D converter; and the internal A / D converter comprises a latch, which maintains the logic state of the multi-phase clock according to the time sequence provided by the comparison output signal and a counter, which counts the clock having the largest width of the plurality of clocks and stops counting according to the comparator.

Description

[0001] This application is a Chinese invention patent application submitted on April 8, 2020, with the application number 201880065606.X, and the title of the invention is "Time Domain A / D Converter Group and Sensor Device Using the Time Domain A / D Converter" divisional application. technical field [0002] The present disclosure relates to a time domain A / D converter and a sensor device using the time domain A / D converter. More specifically, it relates to a time-domain A / D converter, which has: an input signal level determination part; a plurality of reference signal generation circuits, at least one of which generates a signal capable of converting The reference signal of the full-scale (Full Scale) input signal, one of the other reference voltage generation circuits generates a reference signal that periodically scans the limited voltage range multiple times and performs averaging processing; or a delay-locked loop circuit, the delay-locked loop The circuit is used to outp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/56
CPCH03M1/56H03M1/002H03M1/1225H03M1/20
Inventor 松泽昭野原正也
Owner TECH IDEA CO LTD
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