Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Preparation process of solar cell

A solar cell and preparation process technology, applied in the field of solar cells, can solve the problems of affecting the current of the solar cell, serious absorption, etc., and achieve the effects of simple and feasible process, increasing open circuit voltage, and reducing contact minority carrier recombination

Inactive Publication Date: 2020-04-24
JA SOLAR +1
View PDF11 Cites 9 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the disadvantage of this P-type passivated contact cell is that the doped polysilicon layer absorbs the incident light more seriously, and the generated electron-hole pairs recombine in a large number in the polysilicon layer, which affects the current of the solar cell.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Preparation process of solar cell
  • Preparation process of solar cell
  • Preparation process of solar cell

Examples

Experimental program
Comparison scheme
Effect test

preparation example Construction

[0076] In the preparation process of the above-mentioned solar cell:

[0077] The silicon substrate 1 described in step S1 is a P-type silicon wafer. Before step S1, the preparation method further includes: texturizing the silicon substrate 1 and forming a P-N junction 2, and then forming a P-N junction 2. A tunneling passivation layer 3 is provided on at least one surface of the silicon substrate; in step S1 , an intrinsic silicon layer 4 is provided on the tunneling passivation layer 3 .

[0078] Specifically can include:

[0079] Preferably, the silicon substrate 1 in step S1 is a P-type silicon wafer.

[0080] Before the silicon substrate 1 is provided with a doped silicon layer, the silicon substrate is textured and a P-N junction is formed. The P-N junction can be formed by thermal diffusion, ion implantation and annealing. For P-type silicon wafers, the diffusion is phosphorus diffusion,

[0081] After the P-N junction 2 is made, the back of the silicon substrate is...

Embodiment 1

[0106] This embodiment provides a PERC cell with a local Topcon contact structure on the light-receiving surface. In this solar cell, a local doped silicon structure is arranged on the light-receiving surface of the PERC cell. The preparation steps are as follows:

[0107] A. Surface texturing: Provide silicon substrate 1, choose P-type monocrystalline silicon wafer for silicon substrate 1, its volume resistivity is 2.0Ω·cm, complete the surface texturing of silicon wafer, and the surface reflectance of single crystal silicon wafer is 13%;

[0108] B. Clean silicon wafers to prepare P-N junctions: P-N junctions 2 are prepared by furnace tube phosphorus diffusion, and the emitter square resistance is 80-100Ω / □;

[0109] C. Leveling the back surface of the silicon wafer: corrode the back surface in a mixed solution of nitric acid, sulfuric acid and hydrofluoric acid to reduce the specific surface area of ​​the back surface of the silicon wafer, and remove the front phosphosilicat...

Embodiment 2

[0121] This embodiment provides a double-sided partial Topcon cell, that is, a local doped silicon structure is arranged on the front and back of the solar cell. The preparation steps of the double-sided partial Topcon cell are as follows:

[0122] A. Surface texturing: Provide silicon substrate 1, choose P-type monocrystalline silicon wafer for silicon substrate 1, its volume resistivity is 2.0Ω·cm, complete the surface texturing of silicon wafer, and the surface reflectance of single crystal silicon wafer is 13%;

[0123] B. Cleaning silicon wafers to prepare P-N junctions: P-N junctions 2 are obtained by phosphor diffusion in furnace tubes, and the emitter square resistance is 80-100 Ω / □;

[0124] C. Leveling the back surface of the silicon wafer: corrode the back surface in a mixed solution of nitric acid, sulfuric acid and hydrofluoric acid to reduce the specific surface area of ​​the back surface of the silicon wafer, and remove the front phosphosilicate glass layer (PSG)...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
widthaaaaaaaaaa
electrical resistivityaaaaaaaaaa
Login to View More

Abstract

The invention discloses a preparation process of a solar cell. The preparation process comprises the steps of S1 arranging a doped silicon layer on at least one surface of a silicon substrate; S2 setting a coating on a preset region of the doped silicon layer; and S3 removing the doped silicon layer which is not provided with the coating area, and forming a local doped silicon layer on at least one surface of the silicon substrate. According to the process, the silicon layer is locally doped by the coating, and the process is simple and feasible.

Description

technical field [0001] The invention belongs to the technical field of solar cells, and in particular relates to a preparation process of solar cells. Background technique [0002] The crystalline silicon PERC cell structure is the mainstream direction of silicon-based solar cell technology development. For PERC battery technology, the excellent passivation of the aluminum oxide film on the back surface of the P-type battery makes it very responsive to long-wave light, and the photoelectric conversion efficiency of this battery can reach more than 22%. At this time, the severe minority carrier recombination at the contact between the metal electrode and the silicon wafer on the light-receiving surface (front side, also called the front surface) of the battery sheet becomes a bottleneck that limits the further improvement of the battery efficiency. Therefore, trying to reduce or even eliminate the contact area between the metal on the light-receiving surface and the semicond...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/18
CPCH01L31/18H01L31/186H01L31/1868Y02P70/50Y02E10/50
Inventor 陈孝业蒋秀林
Owner JA SOLAR
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com