Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and the preparation method comprises the following steps: 1), providing a semiconductor substrate, and forming a trench in the semiconductor substrate; 2) performing ion implantation on the bottom and the side wall of the trench to form a doped dielectric layer; 3) forming a first dielectric layer in the trench, wherein the upper surface of the first dielectric layer is lower than the upper surface of the semiconductor substrate; 4) growing a substrate extension layer located above the first dielectric layer onthe side wall, which is not covered by the first dielectric layer, of the trench, and exposing a part of the surface of the first dielectric layer; and 5) forming a second dielectric layer at least filling the trench on the surfaces of the first dielectric layer and the substrate extension layer. According to the shallow trench isolation structure, the substrate extension layer is formed to coverthe side wall of the dielectric layer at the edge of the protection trench, so that the formation of an edge gap defect is avoided, the area of an active region is increased, and the narrow channel effect is reduced; a shallow trench isolation structure with a wide trench bottom is obtained through ion implantation, the isolation effect is improved, and the product yield is improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor structure and a preparation method. Background technique [0002] At present, Shallow Trench Isolation (STI) is widely used in the isolation process of 0.25um and below semiconductor technology nodes. Among them, the defects or parameters affecting the performance of the shallow trench isolation structure mainly include edge notch (divot) and the bottom width of the shallow trench isolation structure. In the prior art, the edge of the shallow trench isolation structure is often corroded in the subsequent wet etching to form edge notch defects, thereby causing device failure; in addition, as the device size decreases, the shallow trench isolation structure The bottom width of the transistor and the channel width of the transistor are also reduced, which also seriously affects the electrical performance of the device. [0003] Therefor...

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Problems solved by technology

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a semiconductor structure and a preparation method for solving the problem of poor isolation effect of the shallow trench isolation structure in the prior art

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