Fast Fourier transform hardware design method based on base 2-2 algorithm

Abstract

The invention relates to a base 2-. According to the fast Fourier transform hardware design method of the 2 algorithm, a frequency domain extraction mode is adopted, 16-point FFT of a base 22 algorithm of frequency domain extraction is obtained, a 16-point data flow diagram is obtained, and an overall structure of the base 22 FFT of 16 points based on a serial butterfly unit is designed; The structure comprises four processing stages, and each stage comprises a processing unit and an inverted sequence unit; Wherein the processing unit comprises a butterfly unit and a rotation factor multiplierunit. Each butterfly unit only comprises two adders, a serial butterfly unit of a real number adder and a subtracter is adopted, calculation is completed through two clock periods, addition and subtraction of a real part and an imaginary part are completed respectively, and a simple rotation factor multiplier and a complex rotation factor multiplier unit are designed for an odd number processingstage and an even number processing stage respectively.

Description

technical field [0001] The invention belongs to the category of VLSI (Very Large Scale Integration, referred to as VLSI) design, and relates to a 16-point base 2 2 The VLSI structure of the fast Fourier transform of the algorithm structure. Background technique [0002] Fast Fourier Transform (FFT) has become one of the most important algorithms in signal processing and is widely used in communication, filtering, and digital spectrum analysis. In order to meet the real-time requirements of digital signal processing, many hardware-implemented FFT structures have been proposed to improve the processing speed and reduce the usage of hardware resources. [0003] The pipeline FFT structure is one of the most common FFT hardware structures. This structure can use less hardware resources and process incoming data continuously without interruption. There are currently two FFTs with pipeline structures: a serial pipeline structure, which processes 1 sample point data per clock cyc...

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Problems solved by technology

Use other algorithms, such as in the paper "Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs" by Zhou and Hwang [4] Medium, base 4 and base 2 2 The algorithm improves the usage of the twiddle factor complex multiplier unit, but not the butterfly unit

In Liu and Yu's paper "Apipelined architecture for normal I / O order FFT" [5] Among them, the use of the single-way delay commutator (Single Delay Commutator, SDC) improves the utilization rate of the twiddle factor complex multiplier unit and the butterfly unit, but this structure increases the storage unit

Wang and Liu in the paper "A Combined SDC-SDF Architecture for Normal I / O Pipelined Radix-2" [6] A pipeline structure combining SDF and SDC is proposed in the paper, which can time-division multiplex multipliers and adders, which improves the calculation speed, but consumes a lot of hardware resources

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