Composite grid IGBT chip with three-dimensional channel

Abstract

The invention discloses a composite grid IGBT chip with a three-dimensional channel. The chip includes multiple cells. Each of the cells includes: a trench polysilicon gate electrode located in an intermediate area of the cell; a first oxide layer surrounding the trench polysilicon gate electrode; P well areas formed by injecting P type impurities into the cell on both side areas of a trench; doping areas formed by injecting impurities into the P well areas on both sides of the trench, wherein the width of the doping areas is smaller than the width of the P well areas, and the doping areas include an N++ doping area and a P++ doping area; second oxide layers are located on two side areas, being on the cell, of the doping areas, wherein the second oxide layers are used for covering the surface of the two side areas of the two P well areas, the surface of the P well areas without the doping areas, and partial doping areas; planar polysilicon gate electrodes formed on the second oxide layers; and third oxide layers covering the planar polysilicon gate electrodes. The chip can enable the electric current density of the IGBT chip to be improved, so as to reduce a conducting voltage drop.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a composite gate IGBT chip with a three-dimensional channel. Background technique [0002] Since the advent of IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) devices around 1980, due to the characteristics of bipolar transistor on-state voltage drop and high current density, and MOSFET (Metal-Oxide-Semiconductor Field -Effect Transistor, Metal-Oxide Semiconductor Field Effect Transistor) has high input impedance and fast response, and is widely used in rail transit, smart grid, industrial frequency conversion and new energy development and other fields. [0003] figure 1 It is a schematic cross-sectional view of a half cell of an IGBT chip with a planar gate structure in the prior art. Such as figure 1 As shown, it mainly includes: substrate 101, N well region 102, P well region 103, N+ doped region 104, P+ doped region 105, planar ga...

AI Technical Summary

Problems solved by technology

[0006] figure 2 and image 3 The bottom of the trench gate has a certain limit on the resistance capacity of the IGBT chip

its with figure 1 Compared with the IGBT chip with a planar gate structure shown in the figure, while improving the performance of the IGBT chip, it also sacrifices part of the withstand voltage and solid performance of the planar gate.

Images