Capacitor array structure and manufacturing method thereof

Abstract

The invention provides a capacitor array structure and a manufacturing method thereof. The method comprises steps: 1) a semiconductor substrate is provided, and a laminated structure is formed on thesemiconductor substrate; 2) a patterned mask layer is formed on the laminated structure and multiple capacitor holes are etched in the laminated structure based on the patterned mask layer; 3) a lowerelectrode layer is formed on the bottom part and the side wall of the capacitor hole, and a supporting layer is connected with the lower electrode layer; 4) a sacrificial layer is removed; 5) a nitrogen ion plasma diffusion process is carried out on the lower electrode layer, and the nitrogen ions are diffused to the inner surface and the outer surface of the lower electrode layer; and 6) a capacitive dielectric layer is formed on the inner surface and the outer surface of the lower electrode layer and an upper electrode layer is formed on the outer surface of the capacitive dielectric layer.Through carrying out nitrogen ion plasma diffusion process processing on the lower electrode layer, the electrical connection stability and the charge storage capacity of the capacitor can be effectively improved, and the electricity leakage rate of the capacitor is also reduced.

Description

technical field [0001] The invention belongs to the field of semiconductor device manufacturing, in particular to a method for preparing a capacitor array. Background technique [0002] Dynamic Random Access Memory (DRAM for short) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage. With the continuous evolution of the DRAM process technology, the integration level continues to increase, and the component size continues to shrink. In the current DRAM process below...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a capacitor array structure and its preparation method, which is used to solve the problem of the formation of the by-product chlorine ion doping into the lower electrode layer of the capacitor in the prior art. Electrode layer, leading to problems of reduced stability of the electrical connection of the capacitor, increased leakage rate of the capacitor, and reduced ability of the capacitor to store charge

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