A method of manufacturing a semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of void exposure, uncontrolled STI step height, voids, etc., and achieve the effect of improving void problems.

Active Publication Date: 2021-01-26
SEMICON MFG INT (SHANGHAI) CORP +1
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The above two filling processes tend to form voids in the top area of ​​shallow trenches during the filling process. Due to the existence of voids, the subsequent wet process will lead to the exposure of voids, and at the same time, the STI step height cannot be controlled.
[0004] Therefore, a method for improving STI gap filling is proposed to improve the phenomenon of voids when filling shallow trench gaps

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method of manufacturing a semiconductor device
  • A method of manufacturing a semiconductor device
  • A method of manufacturing a semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] figure 1 A process flow diagram for making a semiconductor device according to an embodiment of the present invention; Figure 2A-2G A cross-sectional view of a structure formed in the relevant steps of making a semiconductor device according to an embodiment of the present invention; it will be combined below figure 1 and Figure 2A-2G The manufacturing method of the present invention will be described in detail.

[0032] Step 101 is executed to provide a semiconductor substrate on which a hard mask layer is formed.

[0033] Such as Figure 2A As shown in FIG. 1 , a structural cross-sectional view of a semiconductor substrate 200 and a hard mask layer sequentially formed on the semiconductor substrate 200 is shown in one embodiment of the present invention. The semiconductor substrate 200 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), and germanium-on...

Embodiment 2

[0052] image 3 It is a process flow diagram of manufacturing a semiconductor device according to an embodiment of the present invention; Figures 4A-4H A cross-sectional view of the structure formed in the relevant steps of the manufacturing method for making a semiconductor device according to an embodiment of the present invention; image 3 and Figures 4A-4H The manufacturing method of the present invention will be described in detail.

[0053] Step 301 is executed to provide a semiconductor substrate on which a hard mask layer is formed.

[0054] Such as Figure 4A As shown, a cross-sectional view of the structure of the semiconductor substrate 400 and the hard mask layer sequentially formed on the semiconductor substrate 400 in one embodiment of the present invention is shown. The semiconductor substrate 400 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI)...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to view more

Abstract

The invention provides a manufacturing method for a semiconductor device. The method comprises the steps: providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate;carrying out the patterning of the hard mask layer and the semiconductor substrate, so as to form a shallow trench; forming silicon thin film layers on the hard mask layer and on the bottom and sidewalls of the shallow trench; carrying out the oxygen doping of the part, located on the top side wall of the shallow trench, of the silicon thin film layers, so as to form a silicon oxide film; carrying out the pretreatment of the silicon oxide film on the top side wall of the shallow trench and the non-doped silicon thin film layers on the bottom and side walls of the shallow trenches; and placing oxide in the shallow trench after pretreatment. After the above processing, the method enables the vertical growth rate of the oxide at the bottom of the shallow trench in a vertical direction to befar greater than the lateral growth rate of the oxide on the top side wall of the shallow trench in a horizontal direction, thereby effectively solving a hole problem in STI gap filling.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] As the feature size of integrated circuit devices becomes smaller and smaller, Shallow Trench Isolation (STI) technology has gradually replaced the traditional Local Oxygen Isolation of Silicon (LOCOS) technology to meet the needs of semiconductor development with smaller size and higher integration. STI technology is a process method that forms shallow trenches on a semiconductor substrate and fills the shallow trenches with dielectric materials. As the size limit becomes smaller and smaller, the STI gap-fill process becomes more and more demanding. Currently, high density plasma chemical vapor deposition (HDPCVD) process and high aspect ratio (HARP) oxide filling process are used to fill shallow trenches. [0003] The above two filling processes tend to form voids in the top region of the ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
CPCH01L21/76224
Inventor 杨军邓浩贡禕琪
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products