Power transistor and manufacturing method thereof

Abstract

The invention relates to a power transistor and a manufacturing method thereof. A cell structure of the power transistor comprises a first conductive type of substrate, a second conductive type of well region on the substrate, a first conductive type of source region in the well region and a gate above the well region, wherein the first conductive type and the second conductive type are opposite conductive types, the power transistor is characterized in that the cell structure also comprises a hole current blocking region, the hole current blocking region wraps at least one part of the well region and is in the second conductive type, the doping concentration of the hole blocking region is smaller than the doping concentration of the well region, and the hole current blocking region extends to a part below a gate adjacent to the gate from a part below the gate. By the power transistor, the avalanche tolerance of the power transistor can be improved, the conventional parameter of a device is not affected, and meanwhile, the reliability of the device working in an inductive load environment is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a power transistor and a method for manufacturing the power transistor. Background technique [0002] Due to the particularity of the use environment and conditions of use, modern electronic circuits have higher and higher requirements for the reliability of power semiconductor devices. Power semiconductor devices (power VDMOS, power IGBT, etc.) are often connected to inductive load circuits due to the needs of use. When the device is turned off, the inductance on the inductive load can generate a voltage twice the power supply voltage applied to the load circuit, which is added between the drain and source of the device, causing the drain and source of the device to withstand a large current impact. When the drain voltage increases and cannot be pinched off, the device enters the avalanche region. At this time, the drain-body diode will generate current carriers, and ...

AI Technical Summary

Problems solved by technology

[0004] 1. Although increasing the implantation dose of the P well can increase the avalanche tolerance, it will increase the turn-on voltage VTH, and more seriously, it will increase the on-resistance Rdon, which will increase the temperature rise of the device, thereby reducing the reliability of the device

[0005] 2. P+ injection after N+ injection will also increase the turn-on voltage VTH, and increase the on-resistance Rdon, which will increase the temperature rise of the device, thereby reducing the reliability of the device

The reason is that the impurity boron ions implanted during this P+ implantation are close to the channel of the device, and the boron ions will diffuse into the channel in the subsequent diffusion process, thereby increasing the turn-on voltage VTH and increasing the on-resistance Rdon

[0006] 3. Increasing the number of cells will increase the area of ​​the chip, thereby increasing the manufacturing cost

[0007] 4. Although P+ implantation after contact hole etching will improve the device burnout caused by poor contact of individual cells in the device, due to the limited size of the contact hole in general, the area of ​​P-type impurities implanted through the contact hole If it is not large enough, the reduction of the resistance Rb of the device body region is limited, so that the improvement of the avalanche resistance is not large enough, so this method is not efficient in improving the avalanche resistance of the device

Images