Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Stacked gate dielectric GaN-based insulated gate high-electron mobility transistor and manufacturing method

A high electron mobility, insulating gate technology, used in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problems of unstable oxygen substitution nitrogen, unstable threshold voltage, negative threshold voltage drift, etc. Activity, improved compatibility, reduced process temperature effects

Inactive Publication Date: 2016-12-14
XIDIAN UNIV
View PDF4 Cites 13 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the surface of nitride materials is very easily oxidized, forming unstable oxygen substitution nitrogen defects in the wurtzite nitride lattice
During the fabrication of insulated gate HEMT devices and the deposition of gate oxide dielectrics, the establishment of a low-quality interface oxide layer causes a high-density interface charge between the gate dielectric layer and the nitride barrier layer, and the charge / discharge effect of the interface state will cause serious threshold Reliability issues such as voltage instability, energy band modulation of interface charges and scattering of remote ionized impurities will cause device performance degradation such as threshold voltage negative drift, channel carrier mobility and transconductance reduction

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Stacked gate dielectric GaN-based insulated gate high-electron mobility transistor and manufacturing method
  • Stacked gate dielectric GaN-based insulated gate high-electron mobility transistor and manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] Embodiment 1, making an AlN dielectric insertion layer 81 with a thickness of 2nm on a sapphire substrate, HfO 2 A GaN-based insulated gate high electron mobility transistor with a high-k dielectric layer 82 having a thickness of 8 nm.

[0033] In step 1, the source electrode 10 and the drain electrode 11 are fabricated on the GaN buffer layer 3 of the epitaxial substrate.

[0034] 1a) Photoetching the region of the source electrode 10 and the region of the drain electrode 11 on the GaN cap layer 6:

[0035] First, bake the epitaxial substrate on a hot plate at 200°C for 5 minutes;

[0036] Then, apply and spin the peeling glue on the GaN cap layer 6, the thickness of the peeling glue is 0.35 μm, and bake the sample on a hot plate at 200°C for 5 minutes;

[0037] Next, apply and spin the photoresist on the stripping adhesive, the thickness of the coating is 0.77 μm, and bake the sample on a hot plate at 90°C for 1 min;

[0038] Afterwards, put the sample that has bee...

Embodiment 2

[0118] Embodiment 2, making an AlN dielectric insertion layer 81 with a thickness of 1 nm on a SiC substrate, Al 2 o 3 The dielectric layer 82 is a GaN-based insulated gate high electron mobility transistor with a thickness of 4nm.

[0119] In step one, the source electrode 10 and the drain electrode 11 are fabricated on the GaN buffer layer 3 of the epitaxial substrate.

[0120] 1.1) Photoetching the region of the source electrode 10 and the region of the drain electrode 11 on the GaN cap layer 6:

[0121] The concrete realization of this step is identical with the step 1a) among the embodiment one;

[0122] 1.2) Evaporate the source electrode 10 and the drain electrode 11 on the GaN cap layer 6 in the region of the source electrode 10 and the region of the drain electrode 11 and on the photoresist outside the region of the source electrode 10 and the region of the drain electrode 11:

[0123] The concrete realization of this step is identical with the step 1b) among the e...

Embodiment 3

[0151] Embodiment 3, making an AlN dielectric insertion layer 81 with a thickness of 1.5nm on a Si substrate, HfO 2 A GaN-based insulated gate high electron mobility transistor with a high-k dielectric layer 82 having a thickness of 6 nm.

[0152] In step A, the source electrode 10 and the drain electrode 11 are formed on the GaN buffer layer 3 of the epitaxial substrate.

[0153] The specific implementation of this step is the same as step 1 in the first embodiment.

[0154] Step B, photoetching the electrical isolation region of the active region on the GaN cap layer 6 , and using an ion implantation process to fabricate the electrical isolation of the active region of the device.

[0155] The specific implementation of this step is the same as step 2 in the second embodiment.

[0156] In step C, a SiN passivation layer 7 is grown on the source electrode 10 , the drain electrode 11 and the GaN cap layer 6 in the active region by PECVD.

[0157] The specific implementation...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a stacked gate dielectric GaN-based insulated gate high-electron mobility transistor, mainly to solve the problem that existing similar devices are low in reliability. The device comprises a substrate (1), an AlN nucleation layer (2), a GaN buffer layer (3), an AlN insertion layer (4), an AlGaN barrier layer (5), a GaN cap layer (6), a SiN passivation layer (7), a gate dielectric layer (8) and a SiN protection layer (9) from bottom to top, wherein two ends of the GaN buffer layer (3) are provided with a source electrode (10) and a drain electrode (11); the middle of the gate dielectric layer (8) is provided with a gate electrode (12); a metal interconnection layer (13) is arranged on the source electrode (10) and the drain electrode (11); and the gate dielectric layer (8) adopts a stacked structure formed by an AlN dielectric insertion layer (81) and a high k dielectric layer (82). The interface characteristics and the gate control capability of the device are improved, the reliability is improved, and the stacked gate dielectric GaN-based insulated gate high-electron mobility transistor can serve as a high-efficiency microwave power device.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, in particular to a high-electron mobility transistor, which can be used to make high-frequency high-power modules. Background technique [0002] Nitride semiconductor materials GaN, AlN, InN and their alloys are the third-generation wide-bandgap semiconductor materials after the first-generation elemental semiconductor materials Si, Ge and the second-generation compound semiconductor materials GaAs, InP, etc., which have a direct bandgap , Wide bandgap width, large continuous adjustable range, high breakdown field strength, fast saturated electron drift speed, high thermal conductivity, and good radiation resistance. With the improvement of technology and social development, the first and second generation semiconductor materials cannot meet the needs of higher frequency and higher power electronic devices. Electronic devices based on nitride semiconductor materials can meet this re...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/778H01L21/335H01L29/423
CPCH01L29/778H01L29/42364H01L29/66462
Inventor 祝杰杰马晓华郝跃杨凌侯斌
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products