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A Tunneling Field Effect Transistor with Increased Current Switching Ratio

A technology of tunneling field effect and current switching ratio, applied in circuits, electrical components, semiconductor devices, etc., can solve the problems of increased leakage current, deterioration of off-state current, etc., to improve on-state current, high on-off ratio, weakened The effect of the bipolar effect

Active Publication Date: 2019-07-19
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Achieving a large on-state current while maintaining a low off-state current TFET, that is, a TFET with a high switching ratio is the goal of the unanimous efforts of researchers. However, the current off-state current of the actual tunneling field effect transistor is relatively large, especially in the short In the case of a channel, the off-state current deteriorates severely, which is mainly due to the tunneling process controlled by the drain in addition to the tunneling process controlled by the gate in the TFET device.
Although there is no gate-controlled tunneling when the device is in the off state, if the drain voltage is too large or the channel is short, tunneling from the source region to the intrinsic region controlled by the drain voltage will occur in the lower part of the source region, and the leakage current will increase. Large, in the case of TFETs made of narrow bandgap, the leakage current problem is more serious
TFETs with high current switching ratio characteristics face great challenges

Method used

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  • A Tunneling Field Effect Transistor with Increased Current Switching Ratio
  • A Tunneling Field Effect Transistor with Increased Current Switching Ratio
  • A Tunneling Field Effect Transistor with Increased Current Switching Ratio

Examples

Experimental program
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Effect test

Embodiment 1

[0037] This example is for figure 1 The shown TFET device structure with increased current switching ratio takes an N-type TFET fabricated on a P-type substrate as an example. This embodiment does not include any method of increasing the on-state current and suppressing the off-state current, which is the simplest combination method.

[0038] The embodiment includes a source region 1, an intrinsic region 2, a drain region 3, a gate oxide layer 4, a source electrode 5, a gate electrode 6, a drain electrode 7, a conductive channel 11, an intrinsic region 12, a P-type high-resistance substrate 15, Isolation groove 16. First select the P-type doped bulk silicon of the (100) crystal plane for epitaxy, and then fabricate the PIN structure; or directly epitaxy a 20nm I layer on the P-type substrate, and then fabricate the PIN structure. Using ion implantation technology to implant B into the source region and implant P into the drain region respectively, to obtain P ++ source reg...

Embodiment 2

[0041] This example is for figure 2 The shown TFET device structure with increased current switching ratio takes an N-type TFET fabricated on a P-type substrate as an example. The N-type doped layer is in contact with the PIN structure above, and the thickness of the N-type doped layer is 200nm. Insulating low K dielectric uses SiO 2 N-type TFET, the relative permittivity is 3.9, and the high-K sidewall uses HfO with a relative permittivity of 22 2 . This embodiment includes all the ways of increasing the on-state current and suppressing the off-state current in the summary of the invention.

[0042] This embodiment includes a source region 1, a drain region 3, a gate oxide layer 4, a source electrode 5, a gate electrode 6, a drain electrode 7, sidewalls 10, a conductive channel 11, an intrinsic region 12, a low-K dielectric region 13, an N-type A doped layer 14, a P-type high-resistance substrate 15, and an isolation groove 16.

[0043] First select the P-type doped bulk ...

Embodiment 3

[0048] This example is for image 3 In the structure of the TFET device with increased current switching ratio shown, an N-type TFET fabricated on Si material is taken as an example. The insulating low-K medium adopts vacuum, and the relative permittivity is 1, that is, there is a cavity in the structure. The high-K sidewall adopts the method of directly depositing a passivation film. The N-type doped layer is in contact with the PIN structure above, and the thickness of the N-type buried layer is 200nm. In this embodiment, high-K dielectric and low-K dielectric are used to increase the on-state current, and PN junction isolation, low-K dielectric, and N-type doped layer are used to suppress the off-state current.

[0049] The embodiment includes source region 1, drain region 3, gate oxide layer 4, source electrode 5, gate electrode 6, drain electrode 7, sidewall 10, polysilicon 11, intrinsic region 12, low-K dielectric region 13, N-type buried layer 14. P-type high-resistan...

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Abstract

The invention belongs to the field of logic devices and circuits in the field of ultra-large-scale integrated circuits, and specifically relates to a tunneling field-effect transistor with an increased current switching ratio. In the present invention, the electric field between the source region and the intrinsic region is increased by setting a low-K dielectric region between the source region and the drain region, thereby increasing the on-state current and suppressing the off-state current. The doped layer and the substrate are set to form a reverse-biased PN junction, and the contact between the source region-low-K dielectric region-drain region and the substrate is isolated, and the off-state current of the TFET is reduced. The above methods of increasing the on-state current and suppressing the off-state can be combined and superimposed on each other. Furthermore, the invention improves the on-state current, is compatible with the traditional CMOS technology, has low cost, and realizes a high current switching ratio.

Description

technical field [0001] The invention belongs to the field of logic devices and circuits in the field of ultra-large-scale integrated circuits, and relates to a longitudinal tunneling TFET device that increases the on-state current, in particular to a tunneling field effect transistor that increases the current switching ratio. Background technique [0002] With the advancement of lithography, implantation and other process technologies, the integration of chips is getting higher and higher, and the power consumption density is also increasing; and as the feature size of MOSFET devices is getting smaller and smaller, the short channel effect, GIDL (gate Drain leakage current) and other effects become serious, which further increases the off-state current. Therefore, the problem of power consumption is one of the main obstacles affecting the development of large-scale integrated circuit chips. [0003] Reducing device leakage is a direct means to reduce integrated circuit pow...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/739H01L29/06
CPCH01L29/0607H01L29/0619H01L29/7391
Inventor 王向展曹建强马阳昊夏琪李竟春
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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