Method for manufacturing self-aligned silicide barrier layer

Abstract

The invention provides a method for manufacturing a self-aligned silicide barrier layer, which is characterized in that dry etching is carried out on the self-aligned silicide barrier layer by adopting the etching power being not greater than 180W and the oxygen flow rate of 5sccm-7sccm, plasma damages in the etching process can be reduced, diffusion of a polymer generated by etching towards the edge of a semiconductor substrate is reduced, and an effect of giving consideration to the etching rate and the etching uniformity is achieved, thereby acquiring a uniform graphical self-aligned silicide barrier layer with excellent performance, avoiding offset of device performance design indicators, and improving the product yield.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a self-aligned silicide barrier layer. Background technique [0002] In the semiconductor device manufacturing process, after forming the semiconductor device layer, it is necessary to form a metal silicide in a specific region to reduce the contact resistance. During this process, a self-aligned silicide block layer (Self-aligned silicide block layer, SAB) is generally required to protect the region on the semiconductor device layer where metal silicide does not need to be formed. The self-aligned silicide schemes widely used in the industry include a silicon oxide SAB layer and a silicon oxide / silicon nitride combined SAB layer. [0003] According to the manufacturing process of semiconductor devices, after the salicide barrier layer is formed, it is subjected to dry plasma etching so as to achieve a preset pattern and thickness. figure 1 ...

AI Technical Summary

Problems solved by technology

During the etching process of the salicide barrier layer in the reaction chamber, if a higher etching power is used, such as greater than 300W, the etching rate of the salicide barrier layer is faster, but this will make the reaction The temperature of the cavity wall and the focus ring 12 (top ring) at the top of the wafer 20 is higher than that of the wafer 20, and the polymer (polymer) produced by etching will diffuse to the edge of the wafer 20, resulting in the middle area and edge of the wafer 20 There is a large thickness difference between the regions, resulting in the inability of the subsequent process to completely remove the self-aligned silicide barrier layer in some regions, making it impossible to form metal silicides in this region, resulting in device failure, or causing plasma to be generated in some device regions Plasma damage, which makes the device performance deviate from the design index (such as threshold voltage shift), which will seriously affect the performance and yield of the final device

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