SRAM storage unit capable of stably working under low voltage

Abstract

The invention discloses an SRAM storage unit capable of stably working under low voltage. The SRAM storage unit comprises two transmission gates, two phase inverters and two NMOS tubes, wherein the two NMOS tubes are connected with each other in series; the two phase inverters and a second transmission gate form a latch; a first storage end of the latch is connected to a data-writing bit line via the first transmission gate; a second storage end of the latch is connected to a grid of a first NMOS tube; a grid of a second NMOS tube is connected to a data-reading word line; a drain of the second NMOS tube is connected to a data-reading bit line. A circuit structure used in the SRAM storage unit is characterized in that data reading and writing word lines are separated and data reading and writing bit lines are separated; a transmission gate is inserted between the output end of a second phase inverter and the input end of a first phase inverter and is used for controlling data writing action; the accurate data writing can be achieved under the condition with low power voltage; the interference on stored data during reading the data can be reduced; the static noise margin of the storage unit can be improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor circuits, and in particular relates to a novel SRAM storage unit which can work stably at a lower voltage. Background technique [0002] Manufacturing cost, operating speed, power consumption and reliability have become the most important indicators of the performance of electronic communication products in today's society. With the continuous improvement of the semiconductor process level, the size of semiconductor devices is continuously reduced. How to achieve the purpose of reducing power consumption by reducing the operating voltage of the circuit has become a major challenge in the design of integrated circuits. Random static memory (SRAM) is a very important part of the SoC system. Due to the reliability of read and write operations, the traditional 6-tube SRAM memory unit determines that its minimum operating voltage is difficult to continue to shrink as the manufacturing process adv...

AI Technical Summary

Problems solved by technology

The reduction of static noise margin means that the stored information of the storage unit is easily disturbed when the data is read, resulting in the original stored information being rewritten

[0010] The traditional 6-tube SRAM storage unit can achieve both stability and area cost when the operating voltage is high. Driven by the requirement to reduce power consumption, as the minimum operating voltage gradually decreases, it is difficult for the storage unit to be written into data or Writing data fails, and as the VDD drops, the static noise margin also drops, and the stability of the memory cell is threatened under low voltage conditions

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