NLDMOS device and manufacture method thereof
A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as low on-resistance, reduce device breakdown voltage, etc., achieve large relative permittivity, improve breakdown Voltage, the effect of reducing the electric field strength
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0047] Such as figure 2 Shown is a schematic structural diagram of the NLDMOS device of the embodiment of the present invention; the NLDMOS device of the embodiment of the present invention includes:
[0048] The N-type doped drift region 108 is formed in the P-type semiconductor substrate 101 . Preferably, the semiconductor substrate 101 is a silicon substrate. A P-type epitaxial layer 103 is formed on the surface of the P-type semiconductor substrate 101, an N-type buried layer 102 is formed at the bottom of the P-type epitaxial layer 103, and the drift region 108 and the subsequent P well 107 are all formed in the P-type epitaxial layer 103. In the P-type epitaxial layer 103.
[0049] The P-well 107 is formed in the P-type semiconductor substrate 101 , and the side of the P-well 107 and the drift region 108 are in contact or separated by a certain distance.
[0050] The polysilicon gate 110 formed above the semiconductor substrate 101, the polysilicon gate 110 is isolat...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com