Manufacturing method of fan-out type packaging structure

Abstract

The invention provides a manufacturing method of a fan-out type packaging structure. A protection layer covers the front surface of a wafer and then the wafer is cut into single chips; the chips are positively adhered on a bearing piece on which a temporary bonding film is coated; then a first insulating resin layer covers the temporary bonding film and the chips, and the first insulating resin layer is higher than the protection layer on the chips; the first insulating resin layer is thinned; then the protection layer is removed and the front surfaces of the chips and electrodes are exposed; then a second insulating resin layer is coated and an opening is formed; a heavy wiring layer is manufactured; then a third insulating resin layer is coated and an opening is formed so that the welding disc of the heavy wiring layer is exposed; conductive columns are formed on the surface of the welding disc; and then the bearing piece and the temporary bonding film are removed, and a protective layer is formed on the first insulating resin layer and the back surfaces of the chips. The packaging structure has no bearing piece so that packaging thickness can be reduced, and application range of the technology can be extended; besides, copper cylinders are not manufactured in the chips so that cost can be reduced.

Description

technical field [0001] The invention relates to a method for manufacturing a fan-out package (FOWLP) structure, and belongs to the technical field of integrated circuit chip packaging. Background technique [0002] With the trend of multi-function and miniaturization of electronic products, high-density microelectronic assembly technology has gradually become the mainstream in the new generation of electronic products. In order to cope with the development of a new generation of electronic products, especially the development of smart phones, PDAs, ultrabooks and other products, the size of chips is developing in the direction of higher density, faster speed, smaller size, and lower cost. The emergence of fan-out wafer-level packaging technology (Fanout Wafer Level Package, FOWLP) has satisfied the characteristics of thinner chip products and saving materials (package substrates), but how to reduce the cost of fan-out wafer-level packaging products has become a need for rese...

AI Technical Summary

Problems solved by technology

[0009] The disadvantage of this technology is that the first insulating resin layer is coated in the third step of the process. Since the thickness of the chip is usually more than 50 microns, the thickness of the coated insulating resin is not easy to control, which is not conducive to the production of fine lines.

[0011] The disadvantage of this technology is that it needs a substrate as a carrier, which increases the complexity of the process and is not conducive to the reduction of the overall thickness of the chip.

Although this technology avoids the use of the second carrier board, the production of copper pillars, the grinding and polishing of the plastic sealing layer, and the control of the outcropping of copper pillars make this technology very expensive

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