Hardware implementation method and system for FEC in OTN system

Abstract

The invention discloses a hardware implementation method and system for a high-throughput FEC in an OTN system and relates to the field of optical fiber communication error control. The method includes the following steps that multiple beats of transmitted data with the bit width of W1 are integrated into one beat of integrated data with the bit width of W2; the beat of integrated data is evenly divided into information code elements of 16 RS code words; the information code elements of the 16 RS code words are coded to obtain 16 coded RS code words; the 16 coded RS code words form OTUk data with the bit width of W2; the OTUk data with the bit width of W2 form multiple beats of OTUK data with the bit width of W1. The high throughput of the whole FEC is realized, meanwhile, the degree of parallelism is reduced when an RS (255, 239) coder is implemented, the hardware resources for implementation of the whole FEC are reduced, the implementation scale is small, the data processing capacity of RS (255, 239) parallel cording can be ensured, and the method and system can be utilized by people conveniently.

Description

technical field [0001] The invention relates to the field of error control of optical fiber communication, in particular to a hardware implementation method and system of a high-throughput FEC (Forward Error Correction, forward error correction) encoder in an OTN (Optical Transport Network, optical transmission network) system. Background technique [0002] In the G.709 of the OTN system interface protocol ITU-T (International Telecommunication Union Telecommunication Standardization Sector), it is recommended to use 16 RS (255, 239) code words (Reed-Solomon code, the code word length is 255 code elements, where the information code There are 239 elements, and there are 16 check symbols) are used as error correction codes for the entire OTN frame after being interleaved and interleaved. see figure 1 As shown, the protocol only stipulates the code pattern used by the error correction code and the interleaving method between codewords, and does not provide the hardware implem...

AI Technical Summary

Problems solved by technology

[0006] However, in actual use, since the bit width requirement of the FEC encoder by the OTN system is usually not an integer multiple of 128, the FEC encoder needs to adopt a larger bit width implementation (that is, the bit width of the FEC encoder is equal to the OTN system requirement The bit width W1 and the least common multiple of 128), its implementation scale is relatively large, and a lot of hardware resources are wasted

[0007] The Chinese invention patent with the publication number CN102882534A discloses a parallel implementation method of RS(n, k) encoding with a parallelism of H. When the parallelism of the RS(255, 239) encoder is 3, since 239 cannot be divisible by 3, Therefore according to the method of this patent, it is necessary to carry out zero padding operation to the unencoded information symbol, and then make the whole code word one beat more than when zero padding is not done, which directly causes the whole parallel coding to reduce the processing ability of valid data (less than 3 yards Yuan / beat), unable to meet the throughput requirements of the entire FEC encoder

Images