Graphene field effect transistor structure and large-scale manufacturing process thereof

Abstract

The invention discloses a graphene field effect transistor structure and a large-scale manufacturing process of the graphene field effect transistor structure. The manufacturing process comprises the steps that firstly, selective growing is carried out on a bottom h-BN dielectric layer and a graphene layer on a catalytic metal thin film layer according to the characteristic of the catalytic metal thin film layer, then photoetching is carried out on the catalytic metal thin film layer, the shape of the bottom h-BN dielectric layer and the graphene layer growing epitaxially is controlled, and finally two-time photoetching on the catalytic metal thin film layer and growing of a top grid h-BN dielectric layer are achieved through structure inversion and connection of two times. The structure comprises the bottom h-BN dielectric layer, the graphene layer and the top grid h-BN dielectric layer, the bottom h-BN dielectric layer, the graphene layer and the top grid h-BN dielectric layer are sequentially arranged from bottom to top, a grid electrode is arranged on the top grid h-BN dielectric layer, and a source electrode and a drain electrode are guided out of the two sides of the graphene layer. According to the graphene field effect transistor structure and the manufacturing process, the problem that an existing process is high in difficulty, low in rate of finished products and poor in product performance is solved, and a good foundation is laid for manufacturing of a graphene-based integrated circuit.

Description

technical field [0001] The invention belongs to the field of semiconductor devices and semiconductor technology. Background technique [0002] Graphene is a two-dimensional material with extremely excellent performance formed by carbon atoms in a hexagonal honeycomb lattice. Its carrier velocity and mobility are much higher than conventional semiconductor materials. It is considered as an integrated circuit material in the post-silicon era. Currently, large-scale graphene wafers can be grown by CVD on catalytic metal substrates and SiC epitaxy. When preparing graphene electronic devices, either the graphene prepared by CVD method needs to be transferred to two SiO / Si (or other) substrates, or the 6H-SiC substrate is directly used as the dielectric layer. These substrates not only The surface has a certain roughness, and there are high-density Coulomb centers in it, coupled with the scattering of optical phonons in the substrate material, the carrier mobility in graphene wil...

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Problems solved by technology

[0003] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a graphene field effect transistor structure, which overcomes the problems of high technological difficulty, low yield and poor performance in the preparation process of large-scale graphene devices at present, for The preparation of graphene-based integrated circuits lays a good foundation

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