Method for manufacturing embedded source/drain MOS transistors

Abstract

The invention provides a method for manufacturing embedded source / drain MOS transistors. The method comprises the steps that gate structures are formed on a PMOS transistor area and an NMOS transistor area formed on a semiconductor substrate respectively; an oxidation barrier layer is deposited; through a nitriding technology and a post-nitridation annealing technology, nitrogen is added to the oxidation barrier layer to form a nitrogen oxidation barrier layer, and a part of the nitrogen oxidation barrier layer is removed to expose the PMOS transistor area or the NMOS transistor area, or after a part of the oxidation barrier layer is removed to expose the PMOS transistor area or the NMOS transistor area, nitrogen is added to the remaining oxidation barrier layer to form the nitrogen oxidation barrier layer through the nitriding technology and the post-nitridation annealing technology; channels adjacent to the two sides of each gate structure are formed in the exposed area; strained silicon materials grow in the channels in an epitaxial mode to form the embedded source / drain MOS transistors. According to the method, the rate of epitaxial growth of the strained silicon materials in the channels is guaranteed, and the risk of pollution to the embedded source / drain MOS transistors can be lowered through the remaining oxidation barrier layer.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a manufacturing method of an embedded source / drain MOS transistor. Background technique [0002] The size of MOS transistors (Metal Oxide Semiconductor Field Effect Transistors) has been continuously reduced over the past few decades. In early semiconductor circuit technology, the channel length in MOS transistors was on the order of several microns. By the end of the 1990s, the size of MOS transistors continued to shrink, which greatly improved the performance of semiconductor circuits. In today's semiconductor circuit technology, this parameter has been reduced by dozens of times or even more than one hundred times. [0003] However, the reduction in the size of MOS transistors also brings some negative problems. For example, a smaller channel width increases the channel equivalent resistance. Therefore, for MOS transistors...

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Problems solved by technology

[0005] However, when the concentration of germanium in silicon germanium is increased in the groove where the source and drain of the PMOS transistor are formed, the number of silicon germanium particles Dot attached to the NMOS transistor will also increase, such as figure 2 as shown, figure 2 It is a schematic top view shown in Figure 1. After cleaning with acidic HCl (hydrogen chloride) gas, although the HCL gas reacts with the silicon germanium attached to the NMOS tube to generate a mixed gas to reduce particles, it will greatly reduce the epitaxial growth rate of silicon germanium.

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