Method for establishing K-value and ten-value half adder and K-value and ten-value half subtracter based on band-pass threshold loading technology and circuit obtained based on method

Abstract

The invention discloses a method for establishing a K-value and ten-value half adder and a K-value and ten-value half subtracter based on the band-pass threshold loading technology and a circuit obtained based on the method. According to the method for establishing the K-value and ten-value half adder and the K-value and ten-value half subtracter based on the band-pass threshold loading technology and the circuit obtained based on the method, the band-pass threshold loading technology is adopted, the demands in all stages are processed according to information, and band-pass thresholds required in different stages are loaded to a PMOS tube, so that the band-pass threshold of the PMOS tube can be changed at any time; the K-value half subtracter and the half adder are analyzed, the characteristic that a high-value area and a low-value area are unified is realized, based on the loading technology, two kinds of circuits can be replaced by one kind of circuits, the traditional method achieved based on a K-value logic gate is avoided, and the circuit structure is simplified greatly; the chaotic encryption method and the circuit can be popularized to K values from two values, K-value multiplication and division are replaced by K-value addition and subtraction, and the multiplication-and-division-free chaotic encryption method and circuit for K-value information are obtained. The method for establishing the K-value and ten-value half adder and the K-value and ten-value half subtracter based on the band-pass threshold loading technology and the circuit obtained based on the method are applied to the VLSIs such as the FPGAs, CPLDs, half-custom or full-custom ASICs and memorizers and the technical field of other digital ICs.

Description

(1) Technical field [0001] The invention belongs to the field of digital integrated circuits, in particular to a construction method of a K-value and ten-value half-adder and half-subtractor using band-pass threshold loading technology and a circuit thereof. (2) Background technology [0002] With the rapid development of MOS integrated circuit technology, the scale of integration is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70℅ of silicon Chip area; in programmable logic devices, a large number of programmable internal wiring is also required to connect each logic function block or input / output to complete a specific function circuit, and wiring accounts for a large cost of materials. Reducing wiring costs becomes an important issue. ② From the perspective of information transmission, the use of multi-valued signals can reduce the number of connections; for each co...

AI Technical Summary

Problems solved by technology

[0002] With the rapid development of MOS integrated circuit technology, the scale of integration is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70℅ of silicon chip area; in programmable logic devices, a large number of programmable internal wiring is also required to connect each logic function block or input / output to complete a specific function circuit, and wiring accounts for a large cost of materials

[0004] 1. In the realization of multi-valued circuits (K≥3), the existing semiconductor manufacturing process to control the threshold of MOS transistors has great disadvantages: ① The range of the control threshold is limited (due to the limited concentration of ion implantation), and the range of the control threshold in the process is often Change the performance of the MOS tube, and the realized voltage-type multi-valued circuit is not larger than the 4-valued circuit, and the application of more-valued circuits is difficult

② Only the magnitude of the threshold can be controlled, and the opening properties of the MOS tube cannot be changed (such as high-pass, low-pass, band-pass, band-resistance control threshold), and the multi-valued circuit must have a variety of MOS tubes with threshold-controlling properties to make the circuit structure most optimal. simple

③ It is necessary to add an additional process of ion implantation, and the threshold can only be controlled in the semiconductor manufacturing process, increasing the complexity of the process, and the threshold cannot be controlled by the user

[0005] 2. In the realization of multi-valued circuits, the existing neuron MOS transistor control threshold technology has great disadvantages: ① With the increase of K value, 'the input gate and control gate capacitance of a single neuron MOS transistor occupies the area of ​​the silicon chip' versus 'a single neuron MOS transistor'. The ratio of the MOS tube to the area of ​​the silicon chip is getting bigger and bigger, ten times, a hundred times or higher; ②As the K value increases, the width of the threshold fuzzy area (turning area) of the input gate ΔV 1 'to' Floating Gate Threshold Fuzzy Area (Turning Area) Width ΔV fg ’ ratio (ΔV 1 / ΔV fg =C TOT / C 1 ) is getting bigger and bigger, because ΔV fg is certain, the threshold fuzzy area ΔV of the input gate 1 The wider and wider the width, the lower the signal resolution capability of the input gate K value, and the high requirement for capacitance accuracy, which is not conducive to the reliable realization of multi-valued circuits with large K values; ③ cannot change the threshold control characteristics (such as band pass, band resistance control threshold mode), which is unfavorable to simplify the K value circuit; ④ with the increase of K value, the ratio (C TOT / C 1 ) becomes larger, the capacitance of the input gate and the control gate increases, and the high-frequency performance decreases rapidly; ⑤ With the increase of the K value, the leakage of the floating gate capacitance cannot be omitted, and it is difficult to refresh the multi-valued information

⑥The static power consumption of the neuron CMOS inverter is 0 only for the binary signal. For a large K value, there is a state where the NMOS tube and the PMOS tube are turned on at the same time, and the static power consumption is even greater; the output of the neuron CMOS follower is usually For capacitive loads, the output voltage rises and falls on different tracks, and there is a large hysteresis voltage, which is not conducive to multi-valued circuits.

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