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Vertical channel dual-mechanism conduction nanowire tunneling transistor and preparation method

A vertical channel, dual-mechanism technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems that cannot meet the requirements of system integration applications, low on-state current, and low efficiency of band-band tunneling. Achieve the effects of suppressing leakage current and bipolar effect, steep sub-threshold slope, and high performance

Active Publication Date: 2017-02-15
PEKING UNIV
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, due to the low efficiency of semiconductor band-band tunneling, the on-state current of TFET is lower than that of traditional MOSFETs, which cannot meet the requirements of system integration applications.

Method used

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  • Vertical channel dual-mechanism conduction nanowire tunneling transistor and preparation method
  • Vertical channel dual-mechanism conduction nanowire tunneling transistor and preparation method
  • Vertical channel dual-mechanism conduction nanowire tunneling transistor and preparation method

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Embodiment Construction

[0046] The implementation method of the vertical structure bipolar mixed conduction double gate tunneling transistor described in the present invention will be further described through specific embodiments below in conjunction with the accompanying drawings

[0047] The specific implementation steps are as Figure 2-Figure 6 Shown: (taking N-type devices as an example)

[0048] 1. Ion implantation to the thermionic emission source region (As, 1E15 / cm -2 , 20keV);

[0049] 2. Epitaxial growth tunneling source region, ion implantation (BF 2 , 1E15 / cm -2 , 20keV);

[0050] 3. Epitaxially lightly doped or undoped Si at the tunnel source region, and deposit a layer of Si on it 3 N 4 Film, photolithography, using RIE to deeply etch the vertical channel region, the width of the channel region is 5nm-100nm, such as figure 2 ;

[0051] 4. Form a gate oxide layer (5nm) by thermal oxidation, and then use LPCVD to deposit polysilicon gates of nanowires such as image 3 shown. ...

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Abstract

The invention provides a vertical-channel double-mechanism conduction nano-wire tunneling transistor and a preparation method. The tunneling transistor comprises a hot electron emission source region, a tunneling source region, a channel region, a tunneling drain region and a gate of a nano-wire. The gate is controlled to encircle the channel; band-to-band tunneling happens at the interface of the tunneling source region and the channel region; the hot electron emission source region, the doping type of which is opposite to that of the tunneling source region, is arranged under the tunneling source region; and the electric potential of the tunneling source region is in floating arrangement, and the source terminal potential of a device is added to the hot electron emission source region. Compared with a conventional TFET, the vertical-channel double-mechanism conduction nano-wire tunneling transistor introduces a hot electron emission mechanism besides a tunneling mechanism through the structure design of the device, thereby enlarging the conduction current of the device effectively, meanwhile, keeping steep subthreshold slope, and improving the characteristics of the device substantially. The vertical-channel double-mechanism conduction nano-wire tunneling transistor is simple in preparation process, reduces the production cost greatly, and simplifies the process flow.

Description

technical field [0001] The invention belongs to the field of CMOS ultra-large-scale integrated circuit (ULSI) field-effect transistor logic devices, and in particular relates to a vertical channel dual mechanism conduction nanowire tunneling transistor. Background technique [0002] Since the birth of integrated circuits, microelectronics integration technology has been developing continuously in accordance with "Moore's Law", and the size of semiconductor devices has been continuously reduced. As semiconductor devices enter the deep submicron range, traditional MOSFET devices are limited by the conduction mechanism of self-diffusion drift, and the subthreshold slope is limited by the thermoelectric potential kT / q, which cannot be reduced synchronously with the reduction of device size. As a result, the reduction of leakage current of MOSFET devices cannot meet the requirements of device size reduction, the energy consumption of the entire chip continues to rise, and the pow...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336H01L21/265
CPCH01L29/66931H01L29/7606H01L29/78
Inventor 王超黄如吴春蕾黄芊芊赵阳
Owner PEKING UNIV
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