Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Preparation method of n-channel silicon carbide insulated gate bipolar transistor

A technology of bipolar transistors and silicon carbide, which is applied in the field of microelectronics, can solve the problems of high energy consumption in the epitaxial process, high manufacturing cost, and large on-resistance, so as to save manufacturing cost and time, save resources and energy, and reduce The effect of preparation difficulty

Active Publication Date: 2017-02-08
XIDIAN UNIV
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] 1. The P-type substrate acting as the collector has many defects and large on-resistance
[0007] 2. High preparation cost
For example, SiC epitaxial equipment is expensive, and the epitaxial process consumes a lot of energy, etc.
[0008] 3. It is technically difficult to grow thicker epitaxial layers
For the growth of epitaxial layers with a thickness of 100 μm and above, the process requirements are high, which can only be achieved by top silicon carbide device companies such as Cree in the world. Therefore, the technical bottleneck problem limits the popularization and application of high-power N-channel SiC IGBT. application

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Preparation method of n-channel silicon carbide insulated gate bipolar transistor
  • Preparation method of n-channel silicon carbide insulated gate bipolar transistor
  • Preparation method of n-channel silicon carbide insulated gate bipolar transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] Example 1: Dislocations in the base plane are 10 4 / cm -3 , the substrate concentration is 2×10 14 cm -3 N-channel silicon carbide insulated gate bipolar transistors were prepared on the micropipe-free N-type SiC substrate.

[0032] Step 1: grow epitaxial layer.

[0033] First perform RCA standard cleaning on the N-type silicon carbide substrate 1, and then epitaxially grow on the entire substrate with a thickness of 0.8 μm and a nitrogen ion doping concentration of 2×10 15 cm -3 N-type epitaxial layer 2, such as image 3 a, The epitaxy process conditions are: temperature 1600°C, pressure 100mbar, silane and propane as reaction gas, pure hydrogen as carrier gas, and liquid nitrogen as dopant source.

[0034] Step 2: P well implantation.

[0035] (2.1) Deposit Al with a thickness of 1.5 μm on the entire silicon carbide epitaxial layer by low-pressure chemical vapor deposition as a barrier layer for P-well ion implantation, and then apply glue and photoetch the P-w...

Embodiment 2

[0058] Example 2: Dislocations in the base plane are 10 4 / cm -3 , the substrate concentration is 3×10 14 cm -3 N-channel silicon carbide insulated gate bipolar transistors were prepared on the micropipe-free N-type SiC substrate.

[0059] refer to figure 1 and figure 2 , the implementation steps of this embodiment are as follows:

[0060] Step 1: RCA standard cleaning is performed on the N-type SiC substrate 1 first, and the epitaxial growth thickness on the entire substrate is 1 μm, and the nitrogen ion doping concentration is 5×10 15 cm -3 N-type epitaxial layer 2, such as image 3 a. The process conditions are as follows: temperature is 1600°C, pressure is 100mbar, silane and propane are used as reaction gas, pure hydrogen is used as carrier gas, and liquid nitrogen is used as dopant source.

[0061] The second step: P well injection.

[0062] The specific implementation of this step is the same as step 2 of embodiment 1.

[0063] The third step: apply glue on t...

Embodiment 3

[0073] Dislocations in the basal plane are 10 4 / cm -3 , the substrate concentration is 5×10 14 cm -3 N-channel silicon carbide insulated gate bipolar transistors were prepared on the micropipe-free N-type SiC substrate.

[0074] refer to figure 1 and figure 2 , the implementation steps of this embodiment are as follows:

[0075] Step A: epitaxial layer growth.

[0076] First perform RCA standard cleaning on the N-type silicon carbide substrate 1, and then epitaxially grow the entire substrate with a thickness of 1.4 μm and a nitrogen ion doping concentration of 7×10 15 cm -3 N-type epitaxial layer 2, such as image 3 a, The epitaxy process conditions are: temperature 1600°C, pressure 100mbar, silane and propane as reaction gas, pure hydrogen as carrier gas, and liquid nitrogen as dopant source.

[0077] Step B: P-well implantation.

[0078] The specific implementation of this step is the same as step 2 of embodiment 1.

[0079] Step C: P + Body contact area injec...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a method for manufacturing an N-channel punch-through silicon carbide insulated gate bipolar transistor. The method mainly solves the problem that currently, the manufacturing cost of the silicon carbide insulated gate bipolar transistor is too high. The method includes the implementation steps that first, an N-type silicon carbide substrate with excellent structural performance is selected, and an N-type epitaxial layer is grown on the front face of the substrate in an epitaxial mode; second, a P well region, a P+ body contact region and an N+ emitter region are sequentially formed on the epitaxial layer of the substrate through ion implantation; third, ion implantation of a P+ collector region and high-temperature annealing are performed on the back face of the substrate, and implanted impurities are activated; fourth, an etching gate oxide layer is grown on the front face of the substrate, and a polysilicon gate is deposited; fifth, metal is deposited on the front face and the back face of the substrate respectively, and electrodes are led out. Compared with an existing method, the method for manufacturing the N-channel silicon carbide insulated gate bipolar transistor has the advantages that an over-thick voltage resisting layer does not need to be grown in an epitaxial mode, a large amount of production cost is saved, the technological steps are simplified, and the transistor can be used for an inverter, a switch power supply and a lighting circuit.

Description

technical field [0001] The invention belongs to the field of microelectronic technology, and relates to a method for preparing a semiconductor device, in particular to a punch-through SiC IGBT using a substrate as a voltage-resistant layer, which can be widely used in frequency converters, inverters, switching power supplies, lighting circuits and motors and other fields. [0002] technical background [0003] Silicon carbide insulated gate bipolar transistor, or SiC IGBT, is a new type of high-voltage resistant device developed based on silicon carbide materials. At present, the mainstream solid-state device used in the field of power electronics is Si IGBT, and its turn-off voltage is 0.6-6.5kV. After 30 years of development, Si IGBT has reached the limit of performance and device structure. With the development of new applications such as electric vehicles, photovoltaic and wind energy green energy, and smart grids, a new leap in the performance of power electronic device...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/331
CPCH01L21/26506H01L29/24H01L29/66068
Inventor 郭辉翟华星宋庆文张艺蒙张玉明汤晓燕
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products