Method for manufacturing high-performance double-layer polysilicon bipolar transistor

Abstract

The invention discloses a method for manufacturing a high-performance double-layer polysilicon bipolar transistor. The method comprises the following steps that 1), LOCOS and CVD are adopted to deposit SiO2 to form a composite isolation structure, and high-temperature process time is reduced; 2), the SiO2 is used as an etching stopping layer of base polysilicon, and etching damage is avoided; 3), a composite side wall structure is formed through SiO2 and N+polysilicon, and emitter resistance is reduced. The method has the advantages that on the premise of not lowering the isolation effect, the high-temperature process time is reduced, therefore, a relatively thin epitaxial layer can be adopted, the better microwave performance is obtained, SiO2 is adopted as the etching stopping layer, the etching damage to the silicon epitaxial layer is eliminated, breakdown characteristics are improved, current amplifying coefficients are increased, and noise coefficients are reduced. The composite side wall structure with SiO2 and N+polysilicon is adopted, it can be guaranteed that emitter-base electric isolation is carried out, and meanwhile the emitter resistance is lowered, the current amplifying coefficients are increased, and the noise coefficients are reduced.

Description

technical field [0001] The invention relates to a method for manufacturing a high-performance double-layer polysilicon bipolar transistor, which belongs to the technical field of microelectronic design and manufacture. Background technique [0002] At present, in the field of wired and wireless communication, compound semiconductor devices, such as GaAs HBT or HEMT, SiGe HBT, etc., have high cut-off frequency and low noise figure due to their inherent material characteristics, and are used in low-noise amplifiers and mixers. It has been widely used in circuits such as. Silicon-based devices, due to lower mobility, their high-frequency performance is inferior to the above-mentioned devices, but at the low end of the microwave, in small and medium power amplifiers and mixer applications in RF front-end and baseband circuits, compared with compound low-noise devices , The advantages of silicon-based BJT are low phase noise, mature technology, and low cost, so it has strong mar...

AI Technical Summary

Problems solved by technology

The advantage of the dielectric side wall structure is that the isolation effect is good, and the disadvantage is that the current conduction area of ​​the emitter is reduced, that is, the emitter resistance is increased.

The reason is that for a high-performance double-layer polysilicon BJT, the P+ polysilicon spacing is generally 0.6 μm to 1.0 μm (not too large, too large will increase the base-emitter distance, increase the lateral size of the device, and increase the parasitic resistance of the base) , the width of the sidewall is generally 0.1 μm to 0.3 μm, and the width of the emission area is generally 0.3 μm to 0.6 μm. Such a small width of the emission area introduces a larger emitter resistance, thereby reducing the current amplification factor and increasing the noise figure.

Images