Silicon on insulator (SOI) process-based back gate drain/source semi-floating front gate P type metal-oxide-semiconductor field effect transistor (P-MOSFET) radio frequency switch zero loss device

Abstract

The invention discloses a silicon on insulator (SOI) process-based back gate drain / source semi-floating front gate power-metal-oxide-semiconductor field effect transistor (P-MOSFET) radio frequency switch zero loss device. A drain / source region of a silicon on insulator P-channel metal oxide semiconductor (SOI PMOS) device is transformed, and the junction depth of a source (or drain) region is set to be slightly smaller than the thickness of N-type top silicon, namely an N-type channel region; the back gate drain semi-floating is taken as an example, the junction depth of a source region is deeper, the junction depth of the drain region is set to be slightly smaller than the thickness of P-type top silicon, a parasitic diode is formed, direct current signals applied to a drain electrode are isolated, and by offsetting a body and a back gate, a back gate MOSFET channel is switched-on; according to the structure, impedence under the on state of a front gate MOSFET is adjusted, the radio frequency loss of the front gate MOSFET serving as a switch under the on state is reduced, and even a zero loss radio frequency switch is formed; when the self-heating effect of the device is generated to cause negative impedence of the back gate MOSFET, or when the back gate MOSFET works in an amplification state, a front gate coupling signal can be directly amplified, and energy loss of the front gate under the on state is compensated, so that an ultralow and zero loss radio frequency switch is formed.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and relates to a back-gate-drain / source semi-floating front-gate P-MOSFET (N-type metal-oxide-semiconductor transistor) radio frequency switch zero-loss device based on SOI (semiconductor on insulating layer) technology. Background technique [0002] The SOI PMOS device eliminates the latch-up effect due to the dielectric isolation, and its unique insulating buried layer structure greatly reduces the parasitic effect of the device, greatly improves the performance of the circuit, and has small parasitic capacitance and high integration density. , high speed, simple process, small short channel effect and other advantages, it is widely used in low voltage, low power consumption, high speed, radiation resistance, high temperature resistance and other fields. The structure of a conventional SOI PMOS device is a sandwich structure of an insulating substrate, a buried layer, and a top monocryst...

AI Technical Summary

Problems solved by technology

When the SOI PMOS device works normally, the channel formed by the source-drain conduction is only on the top surface of the N-type channel region, and it is a lateral channel, and the gate field plate covers the gate oxide layer, resulting in high on-state power consumption , the working efficiency of the device is low, and the loss is large when used as a radio frequency switch, which is not conducive to improving the overall performance of the device and system

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