Multiphase non-overlapping clock circuit

Abstract

The invention discloses a multiphase non-overlapping clock circuit which comprises a delay module, a recurrent pulse generation module, a plurality of inverters and a plurality of RS triggers. The input end of the delay module is connected with one input end of the recurrent pulse generation module to serve as an input port of a mater clock. The output end of the delay module is connected to the other input end of the recurrent pulse generation module. The output end of the recurrent pulse generation module is connected to the setting ends of the RS triggers. The input ends of the inverters respectively serve as the input ports of a multiphase clock. The output ends of the inverters are respectively connected to the other input ends of the corresponding RS triggers. The output ends of the RS triggers respectively serve as the output ends of the multiphase non-overlapping clock. The multiphase non-overlapping clock circuit is simple in structure, small in occupied area of a chip, and high in reliability. By means of the circuit, processing can be carried out on the multiphase clock synchronous with the master clock.

Description

technical field [0001] The invention relates to a multiphase clock processing circuit, in particular to a multiphase non-overlapping clock circuit. Background technique [0002] With the continuous improvement of integrated circuit design technology, people require more and more accurate calculation results of integrated circuits, thus requiring more and more accurate control circuits. In the circuit, the same node can establish signal paths with other multiple signal sources through multiple switches. These signal sources may be different nodes in the circuit, or different power supplies. The control circuit must generate certain switching signals to control the connection between the node and the signal source. Other signal sources are connected in an orderly manner. Generally, the switching signals generated by the control circuit can basically make the node connect to other signal sources in time division. The clock is synchronized, so the rising and falling edges of d...

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In this way, the circuit calculation results may be

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