Semiconductor device structure and fabrication method thereof

Abstract

The invention discloses a semiconductor device structure and a fabrication method thereof. The fabrication method comprises the steps of forming at least one continuous gate line on a semiconductor substrate, forming gate sidewalls around the gate line, forming source or drain regions on both sides of the gate line in the semiconductor substrate, forming conducting sidewalls around the outer sides of the gate sidewalls, realizing electrical isolation among devices in a scheduled region, forming gates of corresponding unit devices at an isolated part of the gate line, and forming contacting parts of the corresponding unit devices at isolated parts of the conducting sidewalls. The fabrication method is particularly suitable for fabricating the contacting parts in an integrated circuit.

Description

technical field [0001] The present invention relates to the field of semiconductors, and more particularly, to a semiconductor device structure and a manufacturing method thereof, wherein the contact portion is formed in a self-aligned manner and may have high tensile stress or compressive stress. Background technique [0002] At present, integrated circuits are shrinking day by day, and their feature sizes are getting smaller and smaller and approaching the theoretical limit of the exposure system. Therefore, the imaging of the wafer surface after photolithography will produce serious distortion, that is, optical proximity effect (Optical Proximity Effect, OPE). As the lithography technology faces higher requirements and challenges, a double patterning technology (Double Patterning Technology, DPT) which can enhance the lithography resolution is proposed. Dual patterning technology is equivalent to decomposing a set of high-density circuit patterns into two separate sets o...

AI Technical Summary

Problems solved by technology

For example, since the etching depth on the gate is different from that in the source / drain region, it is easy to cause a short circuit between the contact hole and the gate

In addition, since the etch depth in the source / drain region is deep and the opening is small (that is, has a small aspect ratio), it may cause various process defects such as incomplete etching, voids in the filling metal, etc., thereby Limits process selectivity and leads to increased parasitic resistance

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