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Semiconductor chip

A semiconductor and chip technology, used in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of limited number and capacitance value of on-chip decoupling capacitors, small parasitic inductance, etc.

Active Publication Date: 2015-07-22
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The integrated circuit is also designed with on-chip decoupling capacitors for power supply noise suppression. Compared with the decoupling capacitors on the package and PCB board levels, the parasitic inductance of the on-chip decoupling capacitors is small, and the effective operating frequency can exceed GHz. Due to the constraints of circuit chip size and integrated circuit technology, the number and value of on-chip decoupling capacitors are currently very limited

Method used

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  • Semiconductor chip
  • Semiconductor chip
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Examples

Experimental program
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Effect test

Embodiment 1

[0111] refer to figure 1 , which shows a schematic cross-sectional view of the semiconductor chip 100 . The semiconductor chip 100 includes a semiconductor substrate 101 and a plurality of conductive TSVs penetrating the semiconductor substrate. A circuit area 104 (such as transistors, diodes, not shown in the figure) is disposed on the front surface 102 of the semiconductor substrate 101 . A seal ring 107 surrounds the circuit area 104 of the semiconductor chip, and its main function is to prevent mechanical damage to the chip during dicing, and at the same time shield external electromagnetic interference. A metal wiring layer 105 is disposed on the circuit area 104 . The metal wiring layer 105 includes at least one layer of metal wiring, and adjacent layers of metal wiring are separated by dielectric material layers (not shown in the figure). At present, the commonly used dielectric material is silicon dioxide. In order to reduce the parasitic capacitance, crosstalk, and...

Embodiment 2

[0121] figure 2 It is a schematic cross-sectional view of the semiconductor chip 200, the conductive through-silicon vias (TSVs) penetrating the semiconductor substrate 201 (including ground through-silicon vias (Ground TSV) 208, power supply through-silicon vias (Power TSV) 209 and signal through-silicon vias (Signal through-silicon vias). TSV) 210) form an electrical connection of the metal wiring in the metal wiring layer 205 of the semiconductor chip to the backside surface 203 of the semiconductor substrate. That is, conductive through-silicon vias (TSVs) penetrating the semiconductor substrate 201 form an electrical connection from one side of the semiconductor chip 200 to the opposite side. The metal layers 2102, 2104, 2106, 2108, and 2110 located on the back passivation layer 2101 of the semiconductor substrate are arranged in sequence, and the spaces between the metal layer 2102 and the metal layer 2104, and between the metal layer 2104 and the metal layer 2106 are r...

Embodiment 3

[0125] Explain the situation that a semiconductor chip requires two or more voltages for power supply due to functional and performance requirements, for example, two or more voltages are required to supply power to different functional areas of the semiconductor chip. The values ​​(volts) of these two or more power supply voltages may be the same or different. That is to say, different functional regions of the semiconductor chip may require power supplies of different voltage levels (different voltage values), for example: 5V, 3.3V, 1.8V, 1.2V and so on. It is also possible that although different functional areas of the semiconductor chip require the same power supply voltage level (voltage value), the signal types of different functional areas are different, for example: digital signal area, analog signal area, microwave radio frequency signal area, low-speed signal area , high-speed signal area, etc. The power supplies of different functional areas need to be isolated to...

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Abstract

The invention discloses a semiconductor chip which comprises a semiconductor substrate and a plurality of conductive silicon through holes which pass through the semiconductor substrate, wherein a plate capacitor structure is arranged on the semiconductor substrate. According to the semiconductor chip, the decoupling performance of an ultra wideband of a power distributing network on the chip is improved, the capability of the semiconductor chip of suppressing the generation and the mutual interference of the power supply noise can be improved within a scope of the ultra wideband, and the capability of resisting the noise interference from an external power supply can be realized, and therefore, the performance of the semiconductor chip is improved.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a semiconductor chip capable of reducing power supply noise of integrated circuits. Background technique [0002] With VLSI entering deep sub-micron, the technology node of CMOS process is advancing from 65nm and 45nm to 32nm and 22nm, and CMOS chips have been developing in the direction of low voltage. 2.5V to 1.8V at 90nm, the supply voltage of the core drops from 5V to 1V at 90nm. The chip power supply voltage drops all the way, which leads to the continuous reduction of the power supply noise tolerance that the chip can tolerate, and the chip is more sensitive to the interference of the power supply system in the time domain and frequency domain. On the other hand, the number of transistors contained in integrated circuit chips continues to increase, and more current is required to drive all these transistors to work. At the same time, the transient switching n...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/64H01L23/00H01L23/485
CPCH01L2224/18H01L2224/16H01L2224/13H01L24/18H01L2223/6677H01L2224/04105H01L2224/12105H01L2224/73267H01L2924/00012
Inventor 李宝霞万里兮
Owner NAT CENT FOR ADVANCED PACKAGING
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