Process for eliminating side wall width load effect
A load effect and sidewall technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of high process temperature, low output, increase device thermal budget, etc., to expand the process window and ensure electrical performance. , the effect of eliminating the load effect
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[0025] The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:
[0026] The invention is a process for eliminating the load effect of sidewall width, which is mainly applied to a semiconductor substrate provided with a gate structure, and has a pattern dense area (Dense) and a pattern empty area (Isolation) on the semiconductor substrate.
[0027] like Figure 4-7 As shown, in the silicon oxide-silicon nitride (Oxide-Nitride, ON) sidewall preparation process, the upper surface of the silicon substrate 3 is provided with a gate oxide layer 31, and the gate 33 is provided on the gate oxide 31. The silicon oxide compensation spacer 34 covers the side wall of the gate 33 and the upper surface of part of the gate oxide 31, and the silicon nitride compensation spacer 35 covers the side wall of the silicon oxide compensation spacer 34 and the gate oxide 31 remaining upper surface.
[0028] Firstly, the barrier layer...
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