SiGe HBT (Heterojunction Bipolar Transistor) device strain Si BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and manufacturing method thereof
A technology for integrating devices and devices, which is used in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., and can solve problems such as low mechanical strength, complex preparation process, and incompatibility with wide-ranging applications and development.
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Embodiment 1
[0128] Embodiment 1: SiGe HBT devices, strained Si BiCMOS integrated devices and circuits with a channel length of 22nm are prepared, and the specific steps are as follows:
[0129] Step 1, epitaxial material preparation.
[0130] (1a) Select the doping concentration as 5×10 14 cm -3 A P-type Si sheet as a substrate;
[0131] (1b) Using chemical vapor deposition (CVD), at 600°C, deposit a SiO with a thickness of 300nm on the surface of the epitaxial Si layer. 2 Layer, photolithographic buried layer region, N-type impurities are implanted into the buried layer region to form N-type heavily doped buried layer region;
[0132] (1c) Etch the oxide layer on the surface of the substrate, and use chemical vapor deposition (CVD) to grow an N-type epitaxial Si layer with a thickness of 1.5 μm on the upper Si material at 600 ° C, as a set electrical region, the doping concentration of this layer is 1×10 16 cm -3 ;
[0133] (1d) Deposit a layer of SiO with a thickness of 200nm on ...
Embodiment 2
[0204] Embodiment 2: The SiGe HBT device, the strained Si BiCMOS integrated device and the circuit that the channel length is prepared to be 30nm, the specific steps are as follows:
[0205] Step 1, epitaxial material preparation.
[0206] (1a) Select the doping concentration as 1×10 15 cm -3 A P-type Si sheet as a substrate;
[0207](1b) Using chemical vapor deposition (CVD), at 700 ° C, deposit a SiO with a thickness of 400 nm on the surface of the epitaxial Si layer. 2 Layer, photolithographic buried layer region, N-type impurities are implanted into the buried layer region to form N-type heavily doped buried layer region;
[0208] (1c) Etch the oxide layer on the surface of the substrate, and use chemical vapor deposition (CVD) to grow a layer of N-type epitaxial Si layer with a thickness of 1.8 μm on the upper Si material at 700 ° C, as a set electrical region, the doping concentration of this layer is 5×10 16 cm -3 ;
[0209] (1d) Deposit a layer of SiO with a thi...
Embodiment 3
[0280] Embodiment 3: The SiGe HBT device, the strained Si BiCMOS integrated device and the circuit that the channel length is prepared to be 45nm, the specific steps are as follows:
[0281] Step 1, epitaxial material preparation.
[0282] (1a) Select the doping concentration as 5×10 15 cm -3 A P-type Si sheet as a substrate;
[0283] (1b) Using chemical vapor deposition (CVD), at 800 ° C, deposit a SiO with a thickness of 500 nm on the surface of the epitaxial Si layer. 2 Layer, photolithographic buried layer region, N-type impurities are implanted into the buried layer region to form N-type heavily doped buried layer region;
[0284] (1c) Etch the oxide layer on the surface of the substrate, and use chemical vapor deposition (CVD) to grow a layer of N-type epitaxial Si layer with a thickness of 2.5 μm on the upper Si material at 750 ° C, as a set electrical region, the doping concentration of this layer is 1×10 17 cm -3 ;
[0285] (1d) Deposit a layer of SiO with a th...
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