True single-phase clock dual-mode prescaler with high speed and low power consumption

Abstract

The invention discloses a true single-phase clock dual-mode prescaler with high speed and low power consumption. The prescaler comprises a trigger unit consisting of a plurality of static complementary metal oxide semiconductor (CMOS) D triggers, a mode switching control unit and an adaptive power consumption control unit; the static CMOS D triggers are synchronously triggered, the CK ends of the static CMOS D triggers are connected with an input clock, and the D ends of the static CMOS D triggers are connected with the output of the mode switching control unit; the input of the mode switching control unit is connected with a frequency division and mode control end and the output of the trigger unit; and the input of the adaptive power consumption control unit is connected with a module power-off control word and the output of the mode switching control unit. Specific logic is adopted in the D triggers to reduce capacitive load so as to improve the working speed, the current of a true single-phase clock is reduced from milliamperes to microamperes at the same high speed compared with a current mode logic structure, and the power consumption of the dual-mode prescaler is also reduced by 15 to 50 percent through an adaptive power consumption control mode according to total frequency dividing ratio configuration.

Description

technical field [0001] The invention relates to a frequency synthesizer with a PLL structure, in particular to a high-speed low-power true single-phase clock dual-mode prescaler. Background technique [0002] In a wireless communication system, the receiving system needs to restore the modulated radio frequency or microwave signal to the original signal or data, while in the transmitting system, the signal or data needs to be modulated to radio frequency or microwave frequency for long-distance transmission. In the process of receiving and sending, it is inseparable from the local oscillation signal, down-converting the receiving signal and up-converting the transmitting signal. [0003] The local oscillation signal is usually generated by a frequency synthesizer based on a phase-locked loop. The frequency synthesizer usually includes a voltage-controlled oscillator, a frequency and phase detector with a charge pump, a multi-mode frequency divider, and a loop filter. When t...

AI Technical Summary

Problems solved by technology

The dual-mode frequency divider in the two structures cannot automatically turn off some unused D flip-flops when the frequency division ratio is switched to further reduce power consumption

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