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MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof

A technology of a MOS transistor and a manufacturing method, which is applied to the field of MOS transistors and their manufacturing, can solve the problems of limited electric field improvement, etc., and achieve the effects of increasing carrier mobility, increasing productivity, and increasing driving current.

Active Publication Date: 2012-07-11
锐立平芯微电子(广州)有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, from figure 2 It can also be seen that the asymmetric channel MOS transistor has limited improvement of the electric field at the source and drain of the channel, and it is necessary to further develop a new structure to improve the performance of this MOS transistor to meet the requirements of high response rate and high reliability. Require

Method used

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  • MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof
  • MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof
  • MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof

Examples

Experimental program
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Embodiment 1

[0054] image 3 It is a schematic diagram of the structure of the PMOS transistor in this embodiment. As shown, the PMOS transistors include:

[0055] a semiconductor substrate 100;

[0056] a gate structure 101 on the semiconductor substrate 100;

[0057] a source region 105 and a drain region 106 in the surface of the semiconductor substrate 100 on both sides of the gate structure 101;

[0058] the channel 107 under the gate structure 101;

[0059] One end (drain end) of the channel 107 close to the drain region 106 has a heterogeneous region 108 , and the dielectric constant of the heterogeneous region 108 is greater than that of other regions in the channel 107 .

[0060] Among them, the semiconductor substrate 100 can be a bulk material composed of elemental semiconductors or components, such as silicon or silicon germanium with a single crystal, polycrystalline or amorphous structure, or a bulk material composed of compound semiconductors, such as silicon carbide, in...

Embodiment 2

[0079] Figure 5 It is a flow chart of the manufacturing method of the MOS transistor in the present embodiment, Figure 6 to Figure 12 It is a schematic diagram of the manufacturing method of the MOS transistor in this embodiment.

[0080] As shown in the figure, the manufacturing method of the MOS transistor includes:

[0081] Step S1: see Figure 6 , provide a semiconductor substrate 100, the semiconductor substrate 100 has a dummy gate structure 101', and a source region 105 and a drain region 106 in the surface of the semiconductor substrate on both sides of the dummy gate structure 101', wherein the source region Between 105 and the drain region 106 is a channel 107 , and the dummy gate structure includes: a dummy gate 102 ′, a dummy gate dielectric layer 104 ′, and gate spacers 103 on both sides of the dummy gate.

[0082] The structure on the semiconductor substrate 100 adopts the traditional manufacturing method of an asymmetric channel MOS transistor, and the dopi...

Embodiment 3

[0113] Figure 18 to Figure 19 It is a schematic diagram of the manufacturing method of the MOS transistor in the present embodiment, and the difference from the second embodiment is that a traditional photoresist process is used to form the pattern of the heterogeneous region.

[0114] like Figure 18 As shown, a photoresist layer 301 is formed on the surface of the substrate after removing the dummy gate, and the photoresist layer 301 covers both the inner and outer surfaces of the gate trench 310 .

[0115] like Figure 19 As shown, using a mask plate (MASK) with a heterogeneous region pattern for alignment and exposure, an opening 311 c is formed in the photoresist layer 301 , that is, the heterogeneous region pattern is transferred into the photoresist layer 301 . Afterwards, using the photoresist layer 301 as the heterogeneous region mask layer, etching the dummy gate dielectric layer and the channel part not covered by the heterogeneous region mask layer, forming a he...

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Abstract

The invention provides an MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof. The MOS transistor comprises a semiconductor substrate, a grid structure, a source region, a drain region and a channel, wherein the grid structure is formed on the semiconductor substrate; the source region and the drain region are formed in semiconductor substrate surfaces on both sides of the grid structure; and the groove is formed below the grid structure. The MOS transistor is characterized in that: one end in the channel close to the drain region is provided with a heterogeneous region; and the dielectric constant of the heterogeneous region is higher than those of other regions in the channel. The drain end of the channel of the MOS transistor is provided with the heterogeneous region, and the heterogeneous region is made of a semiconductor material of which the dielectric constant is higher than those of other regions in the channel and is positioned at a drain end, so that a drain end electric field is reduced relatively, and a source end electric field is enhanced relatively. Compared with the conventional asymmetrical groove MOS transistor, the MOS transistor has the advantages that: the carrier mobility of the source end is further increased, so that the driving current of a device can be raised; and the transverse electric field of the drain end is low, so that the phenomenon of drain end breakdown can be further avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a MOS transistor and a manufacturing method thereof. Background technique [0002] With the gradual increase in the demand for high integration and high performance of VLSI, semiconductor technology is developing towards a technology node with a feature size of 22nm or even smaller. In order to solve many technical problems caused by the size reduction of MOS transistors, a variety of different technical routes have been proposed in the industry. Among them, MOS transistors with asymmetric channel structures are conducive to enhancing the lateral electric field at the source end and reducing the lateral electric field at the drain end. In recent years, it has gradually become a research hotspot. [0003] figure 1 It is a schematic structural diagram of a MOS transistor with an asymmetrical channel structure. As shown in the figure, along the direction from the source reg...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06H01L29/43H01L21/336H01L21/28
Inventor 于伟泽尹海洲
Owner 锐立平芯微电子(广州)有限责任公司
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