Substrate structure with high mobility and preparation method thereof

Abstract

The invention discloses a substrate structure with high mobility and the preparation method thereof, and belongs to the technical filed of semi-conductor integration. The substrate structure includes a single crystal silicon substrate, a buffer layer, a potential barrier layer, an indium-gallium-arsenic monocrystal layer, a blocking layer and a germanium monocrystal layer, wherein the buffer layer is placed on the single crystal silicon substrate; the potential barrier layer is placed on the buffer layer; the indium-gallium-arsenic monocrystal layer is placed on the potential barrier layer; the blocking layer is placed on the indium-gallium-arsenic monocrystal layer; and the germanium monocrystal layer is placed on the blocking layer. Through adopting the substrate structure and the preparation method thereof, a CMOS (complementary metal oxide semiconductor) device with high mobility and the combination of indium, gallium, arsenic and germanium can be realized on the silica-based substrate, or other semi-conductor devices with high mobility can be prepared on the indium-gallium-arsenic monocrystal layer and the germanium monocrystal layer, the substrate structure can be used for preparing the silica-based device, and the photoelectric device can be prepared through adopting the potential barrier layer, the monolithic integration of multiple unit semi-conductor devices can be facilitated, the performance can be improved, and the power consumption can be reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor integration, in particular to a high-mobility substrate structure and a preparation method thereof. Background technique [0002] As the core and foundation of the information industry, semiconductor technology is regarded as an important symbol to measure a country's scientific and technological progress and comprehensive national strength. In the past 40 years, silicon-based integration technology has followed Moore's law to increase the working speed of devices, increase integration and reduce costs by reducing the feature size of devices. The feature size of microelectronic devices has been reduced from the micrometer scale to the nanometer scale. However, when the gate length of MOS devices is reduced to 90 nanometers, the thickness of the gate oxide layer will be less than 1.2 nanometers, and the traditional silicon-based microelectronics integration technology begins to face challenge...

AI Technical Summary

Problems solved by technology

However, when the gate length of MOS devices is reduced to 90 nanometers, the thickness of the gate oxide layer will be less than 1.2 nanometers, and the traditional silicon-based microelectronics integration technology begins to face challenges from both physics and technology

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