Forming method of semiconductor device

Abstract

A manufacturing method for a semiconductor device is provided. The method comprises a semiconductor base body, a gate stack layer (110) and a second protective layer are formed on a first insulating layer (102) sequentially. Source / drain regions are formed by performing ion implantation operation to a semiconductor layer (120) after defining a gate electrode region and removing the second protective layer and the gate stack layer (110) outside the gate electrode region, and a stop layer (122), the semiconductor layer (120) and a second insulating layer (124) which covers a sidewall of the semiconductor layer (120) are reserved outside the gate electrode region and a sacrifice layer is exposed. After a second sidewall is formed to at least cover a portion of the exposed sacrifice layer, a first protective layer and the second protective layer are removed to expose the semiconductor layer (120) and the gate stack layer (110). A contact layer (166) is formed on the exposed semiconductor layer (120) and the gate stack layer (110). The first protective layer is exposed by planarization operation, and then the first protective layer, the sacrifice layer, the stop layer (122) and the semiconductor layer (120) are removed by using a first sidewall (142) and the second sidewall as a mask, and thereby a cavity (200) is formed. The first insulating layer (102) is exposed by the cavity (200). The method is facilitated to reduce short channel effect, resistance of the source / drain regions and parasitic capacitance.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a method for forming a semiconductor device. Background technique [0002] As the channel length of MOSFET (Metal Oxide Field Effect Transistor) continues to shorten, a series of effects that can be ignored in the MOSFET long-channel model become more significant and even become the dominant factor affecting performance. This phenomenon is collectively referred to as short-circuit channel effect. The short-channel effect will degrade the electrical performance of the device, such as causing a drop in gate threshold voltage, increased power consumption, and reduced signal-to-noise ratio. [0003] In order to control the short channel effect, people have to dope more impurity elements such as phosphorus and boron into the channel, but this can easily lead to the decrease of carrier mobility in the device channel; The distribution also has the problem that it i...

AI Technical Summary

Problems solved by technology

Thus, as the width (d) of the source-drain region 30 increases, the parasitic capacitance between the source-drain region 30 and the gate 40 and the semiconductor base 20 increases, thus increasing the resistance capacitance Delay or degrade device AC performance

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