Semiconductor device and forming method thereof

Abstract

This application provides a semiconductor device and a method for forming the same. According to an embodiment of the present invention, a semiconductor device includes: a semiconductor substrate; an insulating layer located on the semiconductor substrate; a semiconductor base body located on the insulating layer; and a cavity formed in the In the semiconductor base and the insulating layer; a source and drain region, the source and drain region is connected to the opposite first side of the semiconductor base; a gate, the gate is located on the opposite second side of the semiconductor base; A channel layer is sandwiched between the second side and the cavity; an ultra-steep receding well and a halo ultra-steep well are formed in the channel layer, and the ultra-steep receding well and the halo ultra-steep well are Steeply receding wells have the opposite doping type. It is beneficial to reduce the short channel effect, source and drain region resistance and parasitic capacitance in semiconductor devices, and can adjust the threshold voltage of semiconductor devices.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device and a forming method thereof. Background technique [0002] As the channel length of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) continues to shorten, a series of effects that can be ignored in the MOSFET long channel model become more and more significant, and even become the dominant factor affecting performance. This phenomenon is collectively referred to as short channel effect. The short channel effect is easy to deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in the signal-to-noise ratio. [0003] In order to control the short channel effect, people have to dope more impurity elements such as phosphorus and boron into the channel, but this will easily lead to the decrease of carrier mobility in the channel of ...

AI Technical Summary

Problems solved by technology

As the width (d) of the source-drain region 30 increases, the parasitic capacitance between the source-drain region 30 and the gate 40 and the semiconductor substrate 20 increases, thereby increasing the resistance-capacitance delay, Device AC Performance Degradation

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