Preparation method for epitaxial diode array isolated by double shallow trenches

Abstract

The invention discloses a preparation method for an epitaxial diode array isolated by double shallow trenches. The method includes the following steps: a heavily doped first conductivity type region and a highly doped second conductivity type region are first formed on a substrate, an epitaxial layer is grown, the isolation between work lines of the diode array is then formed by deep trench etching, the isolation between bit lines, which is perpendicular to the deep trench direction, is formed by shallow trench etching, and finally, independent diode array units are formed in regions defined by the deep trench isolation and the shallow trench isolation by the method of ion injection. The invention also provides an inhibition method for the crosstalk current between the neighboring word lines and bit lines, which is based on the epitaxial diode array isolated by the double shallow trenches. The invention is applicable to high-density, high-capacity memories driven by diodes, such as phase change memories, resistive memories, magnetic memories and ferroelectric memories; the method is fully compatible with the conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) technique, the diode array is formed before a peripheral circuit is formed, so that the thermal process of the diode array cannot cause the drift of the peripheral circuit, and the invention solves the technical problem on how to achieve a high-density, high-capacity embedded phase change memory.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and relates to a structure and a preparation method of a nanoscale high-density and large-capacity memory drive diode array, in particular to a preparation method of a double shallow trench isolation epitaxial diode array. Background technique [0002] Phase change memory (PCRAM) is a new generation of non-volatile semiconductor memory that is compatible with CMOS integrated circuits and has emerged with the development of nano-processing technology. When the feature size of the device enters the nanoscale and shrinks, its storage characteristics based on reversible phase change On the scale of a few nanometers, it will show more excellent performance (low power consumption, high speed, etc.), which is superior to the comprehensive performance of the current commercial FLASH storage technology. It is recognized by the industry as a major breakthrough in storage technology after FLASH. The ...

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Problems solved by technology

Due to the reduction in size, the distance between adjacent word lines is also reduced accordingly, and the leakage current between the word lines through the P-type substrate will increase. When a gated word line flows through a large operating current When the pulse is pulsed, the word line that is not selected next to it will be disturbed by the switching noise and cause misoperation. The unevenness of the deep trench depth and the unevenness of the bottom depth of the word line buried layer will increase the signal between adjacent word lines. possibility of interference

At the same time, due to the reduction of the distance between bit lines and the depth of shallow trenches, the large crosstalk current between adjacent bit lines will cause misoperation

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