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A Method of On-Chip Interconnection Based on Crossbar Structure

A crossbar and bus technology, applied in the computing field, can solve problems such as limiting the communication bandwidth between processing elements and shared resources, not being able to obtain authorized processing elements, and affecting the processing rate of system packets, so as to alleviate access contention, ensure parallel execution, The effect of improving the data throughput rate

Inactive Publication Date: 2011-12-21
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the structure of this shared bus only allows a single set of data to be transmitted on the bus at any one time node, thus limiting the communication bandwidth between processing elements and shared resources.
In addition, when multiple processing elements request to use the bus at the same time, due to the above reasons, only one processing element can be authorized at this time node, so the contention problem of bus access will be introduced, and the communication request initiated by the processing element has a lower priority. Low May not be authorized for a long time, so that the processing element will be in a stagnant state for a long time, thus affecting the system package processing rate

Method used

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  • A Method of On-Chip Interconnection Based on Crossbar Structure
  • A Method of On-Chip Interconnection Based on Crossbar Structure
  • A Method of On-Chip Interconnection Based on Crossbar Structure

Examples

Experimental program
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Embodiment 1

[0030] refer to figure 2 An embodiment of the network processor architecture is shown. In this architecture, four packet processing units 202A, 202B, 202C, 202D are included. It should be noted that the present invention is not limited thereto. For example, other embodiments include (but not limited to) six or eight packet processing units; the packet processing units can perform the same or different functions according to the requirements of the system designer. As the core component of network processor packet processing, the packet processing unit frequently exchanges data with other data processing units in the system. The packet processing unit initiates a transaction as the master control end and accesses the target resource.

[0031] as figure 2 As shown, the network processor of this embodiment also includes a variety of typical shared resources. In sequence, the SRAM unit 212 , the DRAM unit 214 , the encryption / decryption authentication unit 216 and the data s...

Embodiment 2

[0052] According to one embodiment, Figure 5 The details of the write bus are shown. The write buses include write data buses 400A, 400B, 400C, and 400D for data transfer, and write ID buses 402A, 402B, 402C, and 402D for transfer of identification information. as Figure 5 As shown, each shared resource is permanently connected to a write ID bus, and each master is coupled to the horizontal write ID bus through an ID multiplexer. The ID multiplexers used to support the crossbar are sequentially 412A, 412B, 412C and 412D. Each multiplexer is controlled by a lightweight write arbiter (WA). The write arbiter monitors the information in the write ID bus and responds to the request for accessing the master. These arbitrators are 422A and 422B in turn. , 422C and 422D.

[0053] exist Figure 5 In the illustrated embodiment, the writing of data is completed through the transmission of the write data bus, and each master control terminal, as a provider of data, is fixedly conne...

Embodiment 3

[0068] According to one embodiment, Figure 7 Shows the details of the read bus. The read buses include read data buses 500A, 500B, 500C, and 500D for data transfer, and read ID buses 502A, 502B, 502C, and 502D for transferring identification information. and Figure 5 The write ID bus is shown similarly, with each shared resource permanently connected to a read ID bus. The difference is that in the read data bus, each shared resource is fixedly connected to a read data bus, and the master control terminal is coupled to the read data bus through a data multiplexer. The read data multiplexers for supporting the crossbar include 512A, 512B, 512C, 512D. Another difference from the write bus is that in order to solve the problem of access competition caused by multiple shared resources returning data to the same master at the same time node, this embodiment also provides a node cache on each crossbar node , that is, a set of data buffer FIFOs is provided for each multiplexer, ...

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Abstract

The invention discloses an on-chip interconnection method based on a crossbar switch structure. The method comprises the following steps of: providing a plurality of groups of parallel buses between a processing element and a shared resource to improve the parallelism of data interaction; separating command buses from data buses; providing individual buses for the data reading and data write-in of each resource target, wherein the buses are respectively named reading buses and writing buses, the reading buses comprise reading data buses and reading identification (ID) buses, and the writing buses comprise writing data buses and writing ID buses; matching the reading ID buses and the writing ID buses which serve as data reading and write-in identification information with the reading data buses and the writing data buses to finish data transmission between the processing element and the shared resource; and respectively providing a group of light arbiters for the command buses, the reading buses and the writing buses, so that various kinds of arbitration algorithms can be provided for a system designer. Moreover, based on the characteristics of independence of the arbiters in the arbitration scheme, system buses can be quite simply expanded, so that the expandability of a network processor system is improved.

Description

technical field [0001] The invention relates to an on-chip interconnection method based on a crossbar switch structure, belonging to the technical field of computing. Background technique [0002] As an application-specific instruction processor for the network application field, the network processor is a special device for data packet processing, which is applied to various tasks in the specific communication field, such as packet processing, protocol analysis, voice / data aggregation, routing lookup, Firewall, QoS (Quality of Service, that is: quality of service), etc. Networking devices such as network processor-based switches and routers are designed to forward network traffic at high rates in the form of packets. One of the most important considerations in handling network traffic is packet throughput. In order to process the packet, the network processor needs to analyze the packet header information in the data packet sent to the device, extract the packet destinati...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
Inventor 李康范勇雷理赵庆贺史江一马佩军郝跃
Owner XIDIAN UNIV
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