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Semiconductor device and method for manufacturing the same

A semiconductor and device technology, applied in the field of semiconductor devices and their manufacturing, to achieve the effect of high conduction breakdown voltage

Inactive Publication Date: 2010-05-26
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the ratio of secondary electrons to secondary holes multiplied by the ratio of secondary holes to electrons exceeds 1, then the secondary electron current and secondary hole current are in a positive feedback relationship and the gate no longer controls the device

Method used

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  • Semiconductor device and method for manufacturing the same
  • Semiconductor device and method for manufacturing the same
  • Semiconductor device and method for manufacturing the same

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0052] figure 1 is a cross-sectional view of the configuration of a semiconductor device according to an embodiment of the present invention. figure 2 is showing figure 1 A plan view of the configuration of the semiconductor device shown. figure 1 corresponds to along figure 2 The cross-sectional view taken along the line B-B'.

[0053] In the present embodiment, the semiconductor device 100 includes a semiconductor substrate 102 (substrate) and a high breakdown voltage MOS transistor 142 (field effect transistor) formed on the semiconductor substrate 102 .

[0054] In this embodiment, the high breakdown voltage MOS transistor 142 includes a channel region 110a having a gate length L formed at the surface of the semiconductor substrate 102, a gate insulating layer 136 formed on the channel region 110a, and a gate The gate electrode 138 and the source electrode 120 and the drain electrode 118 formed at both sides of the gate electrode 138 .

[0055] The high breakdown...

no. 2 example

[0072] Figure 5 is a cross-sectional view showing the configuration of the semiconductor device according to the present embodiment. Figure 6 is showing Figure 5 A plan view of the configuration of the semiconductor device shown. Figure 5 corresponds to along Figure 6 A cross-sectional view taken along the line C-C'.

[0073] In the present embodiment, the substrate of the semiconductor device 110 may be configured such that the semiconductor layer 104 is formed over the semiconductor substrate 102 which is a semiconductor wafer. For example, semiconductor substrate 102 may be a p-type silicon substrate (silicon wafer). For example, semiconductor layer 104 may be an epitaxial layer. In addition, an n-type buried region 106 and an n-type sinker region 108 are formed in the semiconductor substrate 102 and the semiconductor layer 104 of the semiconductor device 100 . Here, n-type sinker region 108 is continuously formed on n-type buried region 106 over a range from n-t...

example 1

[0088] Figure 10 is used to show the distance “A ”Drain current (I d ) and drain-source voltage (V ds ) The graph of the simulation results of the relationship between. Here, the turn-on breakdown voltage corresponds to the drain current (I d ) at which the drain-source voltage (V ds ).

[0089] Assume that gate voltage Vg is 28V and gate length L (distance between n-type drain-side diffusion region 112 and n-type source-side diffusion region 114) of channel region 110a is 4.5 μm in this example. In addition, when viewing a plan view, it is assumed here that the distance between the element isolation insulating layer 134 and the n-type drain side diffusion region 112 is 5 μm. The p-type high-concentration region 140 is formed by doping with boron (B) so that its peak portion has approximately 1×10 18 cm -3 concentration.

[0090]"None" stated in the figure corresponds to the result of the case where p-type high concentration region 140 is not provided. Here, the uni...

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Abstract

The invention provides a semiconductor device and method for manufacturing the same. There is provided a semiconductor device including a field effect transistor. The field effect transistor includes a p-type low concentration region formed over a surface of a substrate, an n-type drain-side diffusion region and an n-type source-side diffusion region formed over a surface of the p-type low concentration region, an element isolation insulating layer, and another element isolation insulating layer. A p-type high concentration region, which has an impurity concentration higher than the impurity concentration of the p-type low concentration region, is formed below the n-type source-side diffusion region in the p-type low concentration region over a range at least from one end, which is opposite to the other end facing to the channel region, of the source-side diffusion region to one end, which is facing to the channel region, of the second element isolation insulating layer, when seen in a plan view.

Description

[0001] This application is based on Japanese Patent Application No. 2008-253343, the contents of which are incorporated herein by reference. technical field [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same. Background technique [0003] Figure 13 The structure of a lateral double diffused metal oxide semiconductor (LDMOS) disclosed in US Patent No. 7,268,045 and Japanese Laid-Open Patent Publication No. 2002-237591 is shown. The LDMOS includes a p-type body region 22 formed in the surface of the n-type well 12; an n-type source region 18 formed in the body region 22; and a drain region 16 formed in the surface of the n-type well 12 , while an element isolation insulating layer 28 is interposed between the body region 22 and the drain region 16 . Here, buried region 30 is formed under source regio...

Claims

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Application Information

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IPC IPC(8): H01L27/088H01L29/78H01L29/06H01L29/36H01L21/82H01L21/336
CPCH01L29/66659H01L29/1083H01L29/7835H01L29/42368H01L29/0696
Inventor 藤井宏基
Owner RENESAS ELECTRONICS CORP
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