NLDMOS device and manufacture method thereof

Abstract

The invention discloses an NLDMOS device. An N-type deep trap is formed at the left portion of a P-type silicon substrate; a P trap is formed in the N-type deep trap; an N trap is formed at the right portion of the P-type silicon substrate; and a P-type silicon substrate interval zone is arranged between the N-type deep trap and the N trap. The invention also discloses a manufacture method of the NLDMOS device. According to the NLDMOS device and the manufacture method thereof, the deep N trap wraps the P trap so as to enable the P trap to be isolated from the substrate; the dimension of the N-type deep trap is reduced to the P trap which is taken as the channel zone of an NLDMOS, it is ensured that the P trap is isolated from the substrate, and the N-type deep trap is not formed at the N trap which is taken as the drifting zone of the NLDMOS, such that the N-type doping concentration in the drifting zone is decreased, and accordingly, the off-BV of the device is increased; and the dimension of the N trap is increased to the portion between the N-type deep trap and a beak, and the N-type doping concentration below a gate oxide layer is increased, such that the on-BV is increased, and at the same time, it is ensured that the on-resistance is not too large.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to an NLDMOS device and a manufacturing method thereof. Background technique [0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) is currently widely used in power management circuits due to its advantages of high voltage resistance, high current drive capability, extremely low power consumption, and integration with CMOS. [0003] There is a 40V isolated NLDMOS (N-type laterally diffused metal oxide semiconductor) device, such as figure 1 As shown, an N-type deep well 102 is formed on a P-type silicon substrate 101, a P well 105 is formed on the left of the N-type deep well 102, and an N well 104 is formed on the right; between the P well 105 and the N well 104, there is N-type deep well 102 spacer, P well 105 right, N well 104 left and P well 105 and N well 104 are formed above the N-type deep well 102 spacer; polysilicon gate 107 is the same as P well The right part of 105, ...

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Problems solved by technology

[0004] figure 1 In the NLDMOS device shown, the N-type deep well 102 and N-well 104 are sometimes shared with other devices, and the doping concentration cannot be changed, while the N-type deep well 102 is thicker and deeper, so it is not easy to be depleted, and the breakdown voltage is not easy to increase , the breakdown voltage of the device can only be improved by changing the device size and structure

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