Method for forming planar thick isolation medium

A technology of isolating media and planarization, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of microwave signal loss, current capacity limitation, limiting device performance and process yield, etc., to ensure flatness, Effect of Reducing Parasitic Capacitance

Inactive Publication Date: 2011-03-16
NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0002] Since silicon microwave devices and integrated circuits are often fabricated on substrates with high conductivity, there are parasitic capacitances between device metal electrodes, interconnect lines and substrates, resulting in microwave signal loss
In the past, the capacitance was generally reduced by reducing the metal area and depositing a thick isolation dielectric on the semiconductor surface. This method is limited by the current capacity in actual work, or at the same time causes serious unevenness on the surface of the silicon wafer, which limits device performance and finished products. Rate

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  • Method for forming planar thick isolation medium
  • Method for forming planar thick isolation medium
  • Method for forming planar thick isolation medium

Examples

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Embodiment 1

[0039] 1) Select an arsenic-doped silicon substrate region with a thickness of 560 μm and a resistivity of ≤0.003Ω·cm, and its silicon epitaxial layer is doped with phosphorus (n-type), with a resistivity of 0.5Ω·cm and a thickness of 1 μm (attached image 3 );

[0040] 2) Oxidative growth of 0.06 μm silicon dioxide under dry oxygen conditions at 920°C (attached Figure 4 );

[0041] 3), using LPCVD process to deposit a layer of silicon nitride with a thickness of 0.1 μm on the surface of the silicon substrate; (attached Figure 5 );

[0042] 4) Coat a layer of photoresist on the surface of the silicon substrate with a thickness of 1.0 μm, and form an array of etching windows with a spacing of 1.0 μm and 1.2 μm by photolithography, and use a reactive ion etching process to etch away the silicon nitride and silicon nitride in the windows. Silicon dioxide; use ICP to etch the silicon in the process window to form a 1.0 μm deep hole, and finally remove the photoresist (attache...

Embodiment 2

[0048] 1) Select an arsenic-doped silicon substrate region with a thickness of 420 μm and a resistivity of ≤0.003Ω·cm, and its silicon epitaxial layer is doped with phosphorus (n-type), with a resistivity of 500Ω·cm and a thickness of 100 μm (attached image 3 );

[0049] 2) Oxidative growth of 0.08 μm silicon dioxide under dry oxygen conditions at 960°C (attached Figure 4 );

[0050] 3), using LPCVD process to deposit a layer of silicon nitride with a thickness of 0.2 μm on the surface of the silicon substrate; (attached Figure 5 );

[0051] 4) Apply a layer of photoresist on the surface of the silicon substrate with a thickness of 1.5 μm, and form an array of etching windows with a spacing of 1.5 μm and 1.4 μm by photolithography, and use a reactive ion etching process to etch away the silicon nitride and silicon nitride in the windows. Silicon dioxide; use ICP to etch the silicon in the process window to form a 100 μm deep hole, and finally remove the photoresist (atta...

Embodiment 3

[0057] 1) Select an arsenic-doped silicon substrate region with a thickness of 380 μm and a resistivity of ≤0.003Ω·cm, and its silicon epitaxial layer is doped with phosphorus (n-type), with a resistivity of 1000Ω·cm and a thickness of 200 μm (attached image 3 );

[0058] 2) Oxidative growth of 0.1 μm silicon dioxide under dry oxygen conditions at 1000°C (attached Figure 4 );

[0059] 3), utilize the LPCVD process to deposit a layer of silicon nitride with a thickness of 0.3 μm on the surface of the silicon substrate; (attached Figure 5 );

[0060] 4) Coat a layer of photoresist on the surface of the silicon substrate with a thickness of 2.5 μm, and form an array of etched windows with a pitch of 2.0 μm and 1.8 μm by photolithography, and use a reactive ion etching process to etch away the silicon nitride and silicon nitride in the windows. Silicon dioxide; use ICP to etch the silicon in the process window to form a 200 μm deep hole, and finally remove the photoresist (a...

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PUM

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Abstract

The invention relates to a method for forming planar thick isolation medium, which is particularly applicable to the development and the production of the silicon microwave power transistor and microwave monolithic integrated circuit. The method for forming the planar thick isolation medium is characterized by comprising the following process steps: (1) etching an deep hole array on the surface of a silicon wafer; (2) oxidizing all the silicon substrates left on the edges of the deep hole into silicon dioxide with the oxidization process; and (3) covering the deep holes with CVD isolation medium to form the thick isolation medium. The invention has the advantages that the thickness of the isolation medium can be adjusted by the etching depth of the deep holes, an isolation medium film which is as thick as the chip can be obtained, the surface flatness of the silicon wafer and the yield of the isolation medium which is finely processed can be ensured, and less capacitance can parasitize on the isolation medium.

Description

technical field [0001] The invention relates to a method for forming a planarized thick isolation medium, which is especially suitable for the development and production of silicon microwave power transistors and microwave monolithic integrated circuits, and belongs to the technical field of semiconductor microelectronic design and manufacture. Background technique [0002] Since silicon microwave devices and integrated circuits are often fabricated on substrates with high conductivity, there are parasitic capacitances between device metal electrodes, interconnect lines and substrates, resulting in microwave signal loss. In the past, the capacitance was generally reduced by reducing the metal area and depositing a thick isolation dielectric on the semiconductor surface. This method is limited by the current capacity in actual work, or at the same time causes serious unevenness on the surface of the silicon wafer, which limits device performance and finished products. Rate. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/76
Inventor 傅义珠盛国兴王佃利刘洪军
Owner NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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