Bit line leakage current compensation circuit for sub-threshold memory cell array

Abstract

The invention relates to a bit line leakage current compensation circuit for a sub-threshold memory cell array. Source terminals respectively provided with a first compensation transistor (P1) and a second compensation transistor (P2) are connected with power supply voltage; gate terminals are connected with respective body terminals and are respectively connected with the input terminals of a first shielded transmission gate (T1) and a second shielded transmission gate (T2) to be used as a bit line terminal and a non-terminal of a bit line; the drain terminals of P1 and P2 are respectively connected with the output terminals of T1 and T2 and are respectively connected with a first logical memory capacitor (CAP1) and a second logical memory capacitor (CAP2) and then are grounded; the body terminals of respective PMOS pipes in T1 and T2 are connected with the gate terminals to be respectively used as the control terminals of T1 and T2; the body terminals of respective NMOS pipes are connected with the gate terminals to be respectively used as the compensation control terminals of T1 and T2; the source terminals of respective PMOS pipes are connected with the drain terminals of the NMOS pipes to the respective input terminals, and the drain terminals of the PMOS pipes are connected with the source terminals of the NMOS pipes to the respective output terminals; the source terminals of a first precharge balanced transistor (P3) and a second precharge balanced transistor (P4) are connected with the power supply voltage, and the drain terminals are respectively connected with the bit line and the non-terminal of the bit line; the source terminal and the drain terminal of a third precharge balanced transistor (P5) are respectively connected with the bit line and the non-terminal of the bit line; and the gate terminals of P3, P4 and P5 connected together are connected to precharge balanced signals.

Description

technical field [0001] The invention relates to a memory cell under a subthreshold working region, in particular to a bit line leakage current compensation circuit for a subthreshold memory cell array, which is mainly used for compensating the leakage current of a memory cell on the same bit line. The internal information of the memory cell dynamically balances the leakage current on the complementary bit line, avoiding the interference of the bit line logic by the data of the memory cell connected in series on the bit line, so that the bit line logic is only affected by the turn-on current of the selected memory cell, thereby enhancing the selected memory The influence of the cell turn-on current on the bit line swing makes it possible to connect a large number of memory cells in series on the same bit line in a subthreshold design, thereby enhancing the capacity and density of the memory cell array. Background technique [0002] Memory cell arrays are an important part of ...

AI Technical Summary

Problems solved by technology

However, this design also introduces a series of problems in the specific implementation process: 1) The ratio of on-off current (Ion / Ioff) is small——in normal design, the ratio of on-off current (Ion / Ioff) is roughly 10 7 , while in the subthreshold design the value is only 10 3 -10 4 ; 2) the number of memory cells connected in series with the same bit line is limited, so that the capacity of the memory cell array is limited and the area loss is large; 3) the bit line swing is small in the read cycle, and the detection tolerance of the sensitive amplifier is small; 4) Performance is susceptible to process variation, etc.

However, the memory cell array is a large-capacity logic component and has high requirements for design density. The above two methods cannot effectively solve the problem of excessive consumption of memory cell array chip area.

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