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Method for testing the stress of side wall of field effect transistor

A field-effect transistor and sidewall technology, which is applied in the field of testing field-effect transistor sidewall stress, can solve problems such as troublesome design and different threshold voltages of transistors, achieve high realizability, and solve the effect of timely detection of sidewall quality

Inactive Publication Date: 2011-01-26
PEKING UNIV
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  • Description
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  • Application Information

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Problems solved by technology

Therefore, when the mechanical characteristics of the sidewall are not understood, the introduction of the sidewall process will cause the threshold voltage of the transistors in each part of the chip to be different, which will bring a lot of trouble to the design.

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  • Method for testing the stress of side wall of field effect transistor
  • Method for testing the stress of side wall of field effect transistor
  • Method for testing the stress of side wall of field effect transistor

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Embodiment Construction

[0026] The preferred embodiment of the present invention is described in more detail below with reference to the accompanying drawings of the present invention.

[0027] 1. Taking the silicon nitride sidewall as an example to illustrate the test method of the transistor sidewall stress of the present invention, the specific test steps are as follows:

[0028] 1. Form a gate structure.

[0029] Use low-pressure chemical vapor deposition (LPCVD) to grow silicon dioxide 20nm and polysilicon 480nm on the substrate silicon, then use photolithography to define the gate area, and use anisotropic reactive ion etching (RIE) to etch the non-gate area polysilicon 480nm and 480nm polysilicon The silicon dioxide is 20nm, and a 500nm step structure is formed on the substrate silicon wafer.

[0030] 2. Form side walls.

[0031] Using low-pressure chemical vapor deposition (LPCVD) 50nm silicon nitride and anisotropic reactive ion etching (RIE) 50nm silicon nitride, silicon nitride sidewalls...

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Abstract

The invention provides a method for testing the stress of side walls of a field effect transistor, belonging to the technical field of the field effect transistor preparation. The method comprises the following steps: steps are prepared on a substrate to form a grating structure; silicon nitride or silicon oxide is prepared on a grating structure, etched in the anisotropism way to form a side wall structure; a releasing area is defined, and the side wall is released to form a nano-beam structure; the material young modulus, material poisson's ratio and thickness of the nano-beam structure areused for respectively obtaining the axial stress in the nano-beam structure before releasing and the stress gradient along the thickness direction before the nano-beam releases by the measured curve curvature radius, the length before curve and the length after curve of the nano-beam structure, thus obtaining the stress of the side wall. The method solves the problem that the side wall structure stress in the strained silicon device research can not be tested, and is beneficial for increasing the design capability of an integrated circuit.

Description

technical field [0001] The invention relates to field effect transistor (MOSFET-Metal Oxide Silicon Field Effect Transistor, MOSFET for short) technology, in particular to a method for testing side wall stress of field effect transistor. Background technique [0002] Microelectronics technology has achieved rapid development driven by application requirements for decades. With the development of integrated circuit technology, the operating frequency and integration of devices have been greatly improved. However, with the continuous expansion of the scale of the circuit system, the performance requirements of the system for the device and the circuit are also getting higher and higher. Traditional materials and structural devices have great limitations in channel mobility. The speed of traditional bulk silicon material devices cannot be broken through, because the low mobility of silicon material itself greatly affects the speed of integrated circuit circuits. The strained ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66G01L1/06H01L29/772
Inventor 陈会军张大成李婷罗葵田大宇李静王颖
Owner PEKING UNIV
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