Preparation method for complementary metal oxide semiconductor element with dual metal grid

A technology of oxide semiconductor and double metal gate, which is applied in the field of manufacturing complementary metal oxide semiconductor components, can solve the problems of strict requirements on material thickness and composition control, complex integration technology and process control, etc.

Active Publication Date: 2009-07-29
UNITED MICROELECTRONICS CORP
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Problems solved by technology

[0004] Dual-function metal gates are either paired with NMOS elements or PMOS elements, which makes the integration technology and process control of related elements more complicated, and the thickness and composition control requirements of each material are also more stringent.

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  • Preparation method for complementary metal oxide semiconductor element with dual metal grid
  • Preparation method for complementary metal oxide semiconductor element with dual metal grid
  • Preparation method for complementary metal oxide semiconductor element with dual metal grid

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Embodiment Construction

[0041] SeeFigure 2 to Figure 8 , Figure 2 to Figure 8 It is a schematic diagram of the first preferred embodiment of the manufacturing method of the CMOS device with dual metal gate provided by the present invention. Such as figure 2 As shown, first, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc. The surface of the substrate 100 defines a first active region 110 and a second active region 110. The active region 112, and a shallow trench isolation (STI) 102 for electrically isolating the first active region 110 and the second active region 112 is formed in the substrate 100. Next, a high dielectric constant (hereinafter referred to as High-K) gate dielectric layer 104, a tantalum carbide (TaC) layer 106, and a polysilicon layer 108 are sequentially formed on the substrate 100. In addition, in the first embodiment, a protective layer (not shown) may be formed between the High-K gate dielect...

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Abstract

The invention discloses a production method of a CMOS element with bimetal grids. The method comprises: a first conductive transistor and a second conductive transistor are formed respectively on a substrate that is provided with a first active area, a second active area and a shallow trench isolation providing an electric isolation; a metal silicide technology is carried out; an internal dielectric layer is formed on the substrate; a first etching technology is carried out; a part of grid of the first conductive transistor is removed and an opening is formed; and a high-dielectric constant gird dielectric layer of the first conductive transistor is exposed on the bottom of the opening, and a first metal layer is formed in the opening.

Description

Technical field [0001] The present invention relates to a method for manufacturing a complementary metal-oxide semiconductor (complementary metal-oxide semiconductor, hereinafter referred to as CMOS) device with a dual metal gate, especially a gate last ) A manufacturing method of a CMOS device with a dual metal gate in the process. Background technique [0002] As the size of CMOS devices continues to shrink, the traditional methods of reducing the gate dielectric layer, such as reducing the thickness of the silicon dioxide layer, to achieve the purpose of optimization are faced with the tunneling effect of electrons. Physical limitation of excessive leakage current. In order to effectively extend the generational evolution of logic devices, high-permittivity (hereinafter referred to as High-K) materials can effectively reduce the physical limit thickness and have the same equivalent oxide thickness (hereinafter referred to as EOT) Therefore, it can effectively reduce the leakag...

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Application Information

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IPC IPC(8): H01L21/8238H01L21/28
Inventor 林建廷程立伟许哲华马光华杨进盛
Owner UNITED MICROELECTRONICS CORP
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