Preparation method for complementary metal oxide semiconductor element with dual metal grid
A technology of oxide semiconductor and double metal gate, which is applied in the field of manufacturing complementary metal oxide semiconductor components, can solve the problems of strict requirements on material thickness and composition control, complex integration technology and process control, etc.
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[0041] SeeFigure 2 to Figure 8 , Figure 2 to Figure 8 It is a schematic diagram of the first preferred embodiment of the manufacturing method of the CMOS device with dual metal gate provided by the present invention. Such as figure 2 As shown, first, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc. The surface of the substrate 100 defines a first active region 110 and a second active region 110. The active region 112, and a shallow trench isolation (STI) 102 for electrically isolating the first active region 110 and the second active region 112 is formed in the substrate 100. Next, a high dielectric constant (hereinafter referred to as High-K) gate dielectric layer 104, a tantalum carbide (TaC) layer 106, and a polysilicon layer 108 are sequentially formed on the substrate 100. In addition, in the first embodiment, a protective layer (not shown) may be formed between the High-K gate dielect...
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