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Method for forming and etching hard mask layer

A hard mask layer, technology to be etched, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc. Effect

Active Publication Date: 2009-05-27
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] The invention provides a method for forming a hard mask layer and an etching method to improve the poor quality of etching patterns caused by loose and rough hard mask layers in the existing etching technology

Method used

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  • Method for forming and etching hard mask layer
  • Method for forming and etching hard mask layer
  • Method for forming and etching hard mask layer

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no. 1 example

[0056] This embodiment introduces a new method for forming a hard mask layer, Figure 5 is a flow chart of the method for forming a hard mask layer according to the first embodiment of the present invention, Figure 6 to Figure 7 In order to illustrate the device cross-sectional view of the first embodiment of the present invention, below in conjunction with Figure 5 to Figure 7 A first embodiment of the present invention will be described in detail.

[0057] Step 501: Provide a substrate.

[0058] The substrate may be a substrate on which a metal oxide semiconductor transistor has been formed, or a substrate on which an underlying metal wiring structure has been formed. Usually its surface already has a layer to be etched.

[0059] Step 502: forming an initial hard mask layer on the substrate.

[0060] Image 6 It is a schematic cross-sectional view of the device after forming the initial hard mask layer in the first embodiment of the present invention, as Image 6 As ...

no. 2 example

[0082] This embodiment introduces an etching method using a hard mask layer, Figure 8 It is a flowchart of the etching method of the second embodiment of the present invention, Figure 9 to Figure 14 In order to illustrate the cross-sectional view of the device of the second embodiment of the present invention, below in conjunction with Figure 8 to Figure 14 A second embodiment of the present invention will be described in detail.

[0083] Step 801: providing a substrate, and a layer to be etched has been formed on the substrate.

[0084] The substrate may be a substrate on which a metal oxide semiconductor transistor has been formed, or a substrate on which an underlying metal wiring structure has been formed.

[0085] The etching method in this embodiment uses a hard mask layer to assist the photoresist to protect and define the etched pattern. Before forming the hard mask layer, usually a layer to be etched is formed on its surface, and the layer to be etched in this e...

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Abstract

The invention discloses a method for forming a hard mask layer, which comprises the following steps: providing a substrate; forming an initial hard mask layer on the substrate; and performing plasma processing on the initial hard mask layer to form the hard mask layer. The invention also correspondingly discloses a method for etching by using the hard mask layer. With the adoption of the method for forming the hard mask layer and the method for etching, a photoetching figure with better quality can be formed, the etching quality is improved, and the consistency of key size of figure subjected to photoetching or etching is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a hard mask layer and an etching method. Background technique [0002] The process of manufacturing semiconductor integrated circuit chips uses batch processing technology to form a large number of various types of complex devices on the same silicon substrate and connect them to each other to have complete electronic functions. With the rapid development of ultra-large-scale integrated circuits, the integration of chips is getting higher and higher, and the size of components is getting smaller and smaller. The various effects caused by the high density and small size of devices have an increasing impact on the results of semiconductor process manufacturing. protrude. [0003] Taking hard mask technology as an example, when the semiconductor process enters 90nm, because the size of lithography is getting smaller and smaller, it is often ...

Claims

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Application Information

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IPC IPC(8): H01L21/033H01L21/027H01L21/3105H01L21/311
Inventor 安辉
Owner SEMICON MFG INT (SHANGHAI) CORP
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