Method for preparing seedless layer package substrate

Abstract

The invention relates to a method for manufacturing a package substrate without a core layer and a conductive structure of the package substrate. The structure manufactured by the method comprises a storey-adding structure which is provided with a first solder mask layer and a second solder mask layer, wherein, a plurality of openings are formed at the first solder mask layer and the second solder mask layer to expose an electric connection gasket of the storey-adding structure, and the structure also comprises a plurality of solder projections formed on the electric connection gasket and a solder layer. Therefore, the package substrate without the core layer manufactured by the invention can provide a shorter conductive path, improves the wiring density of a circuit and reduces the manufacturing procedures, and the thickness of a whole product is reduced to achieve the light, thin and small function.

Description

technical field [0001] The present invention relates to a manufacturing method of a seedless layer packaging substrate and a conductive structure of the packaging substrate. The manufacturing method especially refers to a seedless layer suitable for a structure without through holes, which can increase the circuit wiring density and reduce the manufacturing process. A method for manufacturing a packaging substrate. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually entering the research and development direction of multi-function and high performance. In order to meet the packaging requirements of high integration and miniaturization of semiconductor packages, the packaging substrates provided for multiple active and passive components and circuit connections have gradually evolved from single-layer boards to multi-layer boards. In a limited space, the available wiring area on the packaging substrate can...

AI Technical Summary

Problems solved by technology

As a result, the thickness of the final multilayer substrate cannot be reduced, which is not conducive to the miniaturization trend of semiconductor packaging substrates

When the thickness of the core substrate is less than 60 μm, the manufacture of the multilayer substrate will face severe challenges, and its production yield will also seriously drop

[0007] In addition, the core substrate must form a plurality of plated via holes, and the via holes must be drilled mechanically, so their diameters are often above 100 μm. 50μm, it can be seen that the technology of plated via holes is not conducive to the formation of fine line structures

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