Three-dimensional ladar module with alignment reference insert circuitry

Abstract

A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is relateda Broadening Reissue of U.S. patent application Ser. No. 11 / 706,724, filed Feb. 15, 2007 (now U.S. Pat. No. 7,436,494), which claims priority to U.S. provisional patent applicationProvisional Patent Application No. 60 / 785,135, filed on Mar. 24, 2006, entitled,“Method for Image Jitter Reduction in a Multilayer LADAR Device” and is a continuation-in-partContinuation-in-Part of U.S. patent application Ser. No. 10 / 806,037, filed on Mar. 22, 2004, entitled,“Three-Dimensional Imaging Processing Module Incorporating Stacked Layers Containing Microelectronic Circuitry,”,(now U.S. Pat. No. 7,180,579), issued Feb. 20, 2007 to Ludwig, et al., which claims the benefit of U.S. provisional applicationProvisional Patent Application No. 60,462,677, filed Mar. 28, 2003., all of which areU.S. Provisional Patent Application No. 60,785,135 and U.S. patent application Ser. No. 10 / 806,037 are both incorporated herein by reference and...

AI Technical Summary

Benefits of technology

"The present invention is a photon source, detector array, and processing module that can generate a three-dimensional image on an electronic display from the output of the processing module. The invention uses stacked layers of readout electronics integrated circuit chips to increase detector output processing circuit density and minimize circuit lead length and associated capacitance. The processing module integrates a large detector array with dedicated detector readout circuitry and allows for the resolution of small target features. The multi-layer ROIC processing module provides the circuit speeds and densities required to resolve small target features while simultaneously providing dedicated processing channels for each detector on the detector array. The laser echo data is pre-processed, converted to a digital form, and multiplexed out of the channels to external post-processing circuitry which aligns and interprets the data and converts it to a usable form, such as an electronic representation of 3-D point cloud for display as an electronic image on a screen."

Problems solved by technology

Unfortunately, existing LADAR imaging systems lack the necessary circuit speed and capacity to achieve very high (i.e., centimeter) range resolution and sensitivity.

Nonetheless, these types of sensors are undesirable where accurate scene information in a complex video environment (i.e., camouflaged or partially obscured targets) is an important factor in the observer's decision-making.

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