Three-dimensional ladar module with alignment reference insert circuitry

a three-dimensional ladar module and alignment reference technology, applied in the field of laserradar imaging technology, can solve the problems of undesirable sensor types, lack of circuit speed and capacity to achieve very high (i.e., centimeter) range resolution and sensitivity, etc., to achieve enhanced imaging capability, reduce layer-to-layer or channel-to-channel “jitter”, and increase detector output processing circuit density

Active Publication Date: 2012-10-09
AI-CORE TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0016]In yet a further aspect of the invention, one or more alignment reference points are inserted at a predetermined point in the image capture cycle to allow the electronic alignment of selected sets of image data collected by the FIFO shift registers in the one or more channels in one or more ROICs contained in the processing module. In this aspect of the invention, alignment reference point insertion and alignment circuitry is provided as means to minimize layer-to-layer or channel-to-channel “jitter” which may be present due to variances in layer operating or data capture start-up characteristics. Alternatively, the invention allows a user to selectively insert an alignment reference point in an individual channel.
[0017]The enhanced imaging capability provided by the claimed invention is achieved, in part, by the use of stacked layers containing the ROIC circuitry, which increases detector output processing circuit density while minimizing circuit lead length and associated capacitance. The result of the stacked layers of ROIC circuitry is the ability to integrate a large (e.g., 128×128 or larger) detector array with associated dedicated detector readout circuitry (amplifier, threshold detector, sampling circuitry, analog to digital (ADC), digital to analog converters (DAC) and first in, first out, (FIFO) shift register “range” bins all within a very small module.

Problems solved by technology

Unfortunately, existing LADAR imaging systems lack the necessary circuit speed and capacity to achieve very high (i.e., centimeter) range resolution and sensitivity.
Nonetheless, these types of sensors are undesirable where accurate scene information in a complex video environment (i.e., camouflaged or partially obscured targets) is an important factor in the observer's decision-making.

Method used

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  • Three-dimensional ladar module with alignment reference insert circuitry
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  • Three-dimensional ladar module with alignment reference insert circuitry

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Embodiment Construction

[0033]Turning now to the figures wherein like numerals designate like elements among the several views, FIG. 1 shows a block diagram of the present invention.

[0034]A photon source, such as a laser 1, generates a beam pulse 5, which is directed toward a scene or target 7, through suitable beam-shaping optics 10.

[0035]In a preferred embodiment, laser 1 is a 1064 nm, mechanically aligned, 300 micro-Joule, seed YAG laser capable of producing a pulse width of 500 picoseconds. In the preferred embodiment, a beam amplifier is provided (not shown), such as a master oscillator power amplifier, wherein a seed beam is fed into the amplifier. In this preferred embodiment, the seed beam passes through a Faraday rotator and enters a four-pass, thermally-controlled amplifier which includes two pumped YAG diodes.

[0036]In the preferred embodiment, beam-shaping optics 10 is a beam-shaping holographic lens suitable for projecting a rectangular beam area on a target. It has been determined that a recta...

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Abstract

A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is relateda Broadening Reissue of U.S. patent application Ser. No. 11 / 706,724, filed Feb. 15, 2007 (now U.S. Pat. No. 7,436,494), which claims priority to U.S. provisional patent applicationProvisional Patent Application No. 60 / 785,135, filed on Mar. 24, 2006, entitled,“Method for Image Jitter Reduction in a Multilayer LADAR Device” and is a continuation-in-partContinuation-in-Part of U.S. patent application Ser. No. 10 / 806,037, filed on Mar. 22, 2004, entitled,“Three-Dimensional Imaging Processing Module Incorporating Stacked Layers Containing Microelectronic Circuitry,”,(now U.S. Pat. No. 7,180,579), issued Feb. 20, 2007 to Ludwig, et al., which claims the benefit of U.S. provisional applicationProvisional Patent Application No. 60,462,677, filed Mar. 28, 2003., all of which areU.S. Provisional Patent Application No. 60,785,135 and U.S. patent application Ser. No. 10 / 806,037 are both incorporated herein by reference and...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G01C3/08
CPCG01S7/487G01S7/51G01S17/42G01S7/4863G01S17/894
Inventor KENNEDY, JOHNLUDWIG, DAVIDKRUTZIK, CHRISTIAN
Owner AI-CORE TECH LLC
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